Lines Matching +full:esync +full:- +full:control
1 //===- XtensaInstrInfo.td - Target Description for Xtensa -*- tablegen -*--===//
7 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
71 let imm8 = imm_sh8{15-8};
80 //===----------------------------------------------------------------------===//
82 //===----------------------------------------------------------------------===//
88 let imm8{7-0} = imm{7-0};
89 let s{3-0} = imm{11-8};
102 //===----------------------------------------------------------------------===//
104 //===----------------------------------------------------------------------===//
145 let s = imm1{3-0};
147 let Inst{23-20} = imm2;
156 let s = sa{3-0};
173 let t = sa{3-0};
187 let s = imm{3-0};
188 let t{3-1} = 0;
192 //===----------------------------------------------------------------------===//
194 //===----------------------------------------------------------------------===//
207 let imm8{7-0} = addr{11-4};
208 let s{3-0} = addr{3-0};
227 let imm8{7-0} = addr{11-4};
228 let s{3-0} = addr{3-0};
260 let imm8{7-0} = addr{11-4};
261 let s{3-0} = addr{3-0};
270 //===----------------------------------------------------------------------===//
272 //===----------------------------------------------------------------------===//
401 let r{3-1} = 0x3;
403 let t{3-0} = imm{3-0};
413 let r{3-1} = 0x7;
415 let t{3-0} = imm{3-0};
419 //===----------------------------------------------------------------------===//
421 //===----------------------------------------------------------------------===//
480 //===----------------------------------------------------------------------===//
482 //===----------------------------------------------------------------------===//
499 //===----------------------------------------------------------------------===//
500 // Processor control instructions
501 //===----------------------------------------------------------------------===//
527 def ESYNC : RRR_Inst<0x00, 0x00, 0x00, (outs), (ins),
528 "esync", []> {
553 //===----------------------------------------------------------------------===//
555 //===----------------------------------------------------------------------===//
559 // pointer before prolog-epilog rewriting occurs.
569 //===----------------------------------------------------------------------===//
571 //===----------------------------------------------------------------------===//