1 //===- XtensaISelLowering.cpp - Xtensa DAG Lowering Implementation --------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that Xtensa uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "xtensa-lower"
47   addRegisterClass(MVT::i32, &Xtensa::ARRegClass);  in XtensaTargetLowering()
50   setStackPointerRegisterToSaveRestore(Xtensa::SP);  in XtensaTargetLowering()
113   // The Xtensa target isn't yet aware of offsets.  in isOffsetFoldingLegal()
117 //===----------------------------------------------------------------------===//
119 //===----------------------------------------------------------------------===//
126   static const MCPhysReg IntRegs[] = {Xtensa::A2, Xtensa::A3, Xtensa::A4,  in CC_Xtensa_Custom()
127                                       Xtensa::A5, Xtensa::A6, Xtensa::A7};  in CC_Xtensa_Custom()
168     if (needs64BitAlign && (Register == Xtensa::A3 || Register == Xtensa::A5 ||  in CC_Xtensa_Custom()
169                             Register == Xtensa::A7))  in CC_Xtensa_Custom()
173     if (needs128BitAlign && (Register != Xtensa::A2))  in CC_Xtensa_Custom()
180     if (Register == Xtensa::A3 || Register == Xtensa::A5 ||  in CC_Xtensa_Custom()
181         Register == Xtensa::A7)  in CC_Xtensa_Custom()
232         RC = &Xtensa::ARRegClass;  in LowerFormalArguments()
241       // If this is an 8 or 16-bit value, it has been passed promoted  in LowerFormalArguments()
326   Align StackAlignment = TFL->getStackAlign();  in LowerCall()
346              "ByVal args of size 0 should have been ignored by front-end.");  in LowerCall()
348              "Do not tail-call optimize if there is a byval argument.");  in LowerCall()
351         StackPtr = DAG.getCopyFromReg(Chain, DL, Xtensa::SP, PtrVT);  in LowerCall()
365       // floats are passed as right-justified 8-byte values.  in LowerCall()
367         StackPtr = DAG.getCopyFromReg(Chain, DL, Xtensa::SP, PtrVT);  in LowerCall()
382   // Build a sequence of copy-to-reg nodes, chained and glued together.  in LowerCall()
395     name = E->getSymbol();  in LowerCall()
396     TF = E->getTargetFlags();  in LowerCall()
398       report_fatal_error("PIC relocations is not supported");  in LowerCall()
400       Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, TF);  in LowerCall()
402     const GlobalValue *GV = G->getGlobal();  in LowerCall()
403     name = GV->getName().str();  in LowerCall()
425   // Add a register mask operand representing the call-preserved registers.  in LowerCall()
427   const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);  in LowerCall()
528     return Xtensa::BEQ;  in getBranchOpcode()
530     return Xtensa::BNE;  in getBranchOpcode()
532     return Xtensa::BLT;  in getBranchOpcode()
534     return Xtensa::BGE;  in getBranchOpcode()
536     return Xtensa::BLT;  in getBranchOpcode()
538     return Xtensa::BGE;  in getBranchOpcode()
540     return Xtensa::BLTU;  in getBranchOpcode()
542     return Xtensa::BGEU;  in getBranchOpcode()
544     return Xtensa::BLTU;  in getBranchOpcode()
546     return Xtensa::BGEU;  in getBranchOpcode()
560   ISD::CondCode CC = cast<CondCodeSDNode>(Op->getOperand(4))->get();  in LowerSELECT_CC()
573   APInt APVal = CN->getAPIntValue();  in LowerImmediate()
577     if (Value > -2048 && Value <= 2047)  in LowerImmediate()
581     if ((OpNode.hasOneUse() && OpNode.use_begin()->getOpcode() == ISD::ADD) &&  in LowerImmediate()
597   const GlobalValue *GV = G->getGlobal();  in LowerGlobalAddress()
608   const BlockAddress *BA = Node->getBlockAddress();  in LowerBlockAddress()
627   SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);  in LowerBR_JT()
630   unsigned EntrySize = MJTI->getEntrySize(TD);  in LowerBR_JT()
650       XtensaConstantPoolJumpTable::Create(*DAG.getContext(), JT->getIndex());  in LowerJumpTable()
669   if (!CP->isMachineConstantPoolEntry()) {  in LowerConstantPool()
670     Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign(),  in LowerConstantPool()
671                                        CP->getOffset());  in LowerConstantPool()
681   return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op), Xtensa::SP,  in LowerSTACKSAVE()
687   return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op), Xtensa::SP,  in LowerSTACKRESTORE()
695   EVT VT = Size->getValueType(0);  in LowerDYNAMIC_STACKALLOC()
704   unsigned SPReg = Xtensa::SP;  in LowerDYNAMIC_STACKALLOC()
760 //===----------------------------------------------------------------------===//
762 //===----------------------------------------------------------------------===//
788   const BasicBlock *LLVM_BB = MBB->getBasicBlock();  in emitSelectCC()
789   MachineFunction::iterator It = ++MBB->getIterator();  in emitSelectCC()
791   MachineFunction *F = MBB->getParent();  in emitSelectCC()
792   MachineBasicBlock *CopyMBB = F->CreateMachineBasicBlock(LLVM_BB);  in emitSelectCC()
793   MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(LLVM_BB);  in emitSelectCC()
795   F->insert(It, CopyMBB);  in emitSelectCC()
796   F->insert(It, SinkMBB);  in emitSelectCC()
799   SinkMBB->splice(SinkMBB->begin(), MBB,  in emitSelectCC()
800                   std::next(MachineBasicBlock::iterator(MI)), MBB->end());  in emitSelectCC()
801   SinkMBB->transferSuccessorsAndUpdatePHIs(MBB);  in emitSelectCC()
803   MBB->addSuccessor(CopyMBB);  in emitSelectCC()
804   MBB->addSuccessor(SinkMBB);  in emitSelectCC()
811   CopyMBB->addSuccessor(SinkMBB);  in emitSelectCC()
817   BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII.get(Xtensa::PHI),  in emitSelectCC()
831   case Xtensa::SELECT:  in EmitInstrWithCustomInserter()