1 //===-- X86TileConfig.cpp - Tile Register Configure----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 /// know the shape of each physical tile registers, because the register
14 /// pass. It collects the shape information of each physical tile register
16 /// to tile config register.
18 //===----------------------------------------------------------------------===//
48   StringRef getPassName() const override { return "Tile Register Configure"; }  in getPassName()
73 INITIALIZE_PASS_BEGIN(X86TileConfig, DEBUG_TYPE, "Tile Register Configure",
76 INITIALIZE_PASS_END(X86TileConfig, DEBUG_TYPE, "Tile Register Configure", false,  in INITIALIZE_PASS_DEPENDENCY()
81   // Early exit in the common case of non-AMX code.  in INITIALIZE_PASS_DEPENDENCY()
82   if (X86FI->getAMXProgModel() != AMXProgModelEnum::ManagedRA)  in INITIALIZE_PASS_DEPENDENCY()
123   unsigned AMXRegNum = TRI->getRegClass(X86::TILERegClassID)->getNumRegs();  in INITIALIZE_PASS_DEPENDENCY()
129     if (MRI.getRegClass(VirtReg)->getID() != X86::TILERegClassID)  in INITIALIZE_PASS_DEPENDENCY()
133     unsigned Index = VRM.getPhys(VirtReg) - X86::TMM0;  in INITIALIZE_PASS_DEPENDENCY()
138   // Fill in the shape of each tile physical register.  in INITIALIZE_PASS_DEPENDENCY()
146     for (auto &R : {Shape.getRow()->getReg(), Shape.getCol()->getReg()}) {  in INITIALIZE_PASS_DEPENDENCY()
147       // Here is the data format for the tile config.  in INITIALIZE_PASS_DEPENDENCY()
150       // 2-15   reserved, must be zero  in INITIALIZE_PASS_DEPENDENCY()
151       // 16-17  tile0.colsb Tile 0 bytes per row.  in INITIALIZE_PASS_DEPENDENCY()
152       // 18-19  tile1.colsb Tile 1 bytes per row.  in INITIALIZE_PASS_DEPENDENCY()
153       // 20-21  tile2.colsb Tile 2 bytes per row.  in INITIALIZE_PASS_DEPENDENCY()
155       // 30-31  tile7.colsb Tile 7 bytes per row.  in INITIALIZE_PASS_DEPENDENCY()
156       // 32-47  reserved, must be zero  in INITIALIZE_PASS_DEPENDENCY()
157       // 48     tile0.rows Tile 0 rows.  in INITIALIZE_PASS_DEPENDENCY()
158       // 49     tile1.rows Tile 1 rows.  in INITIALIZE_PASS_DEPENDENCY()
159       // 50     tile2.rows Tile 2 rows.  in INITIALIZE_PASS_DEPENDENCY()
161       // 55     tile7.rows Tile 7 rows.  in INITIALIZE_PASS_DEPENDENCY()
162       // 56-63  reserved, must be zero  in INITIALIZE_PASS_DEPENDENCY()
165       for (auto &DefMI : MRI.def_instructions(R)) {  in INITIALIZE_PASS_DEPENDENCY()
176                       BuildMI(MF.front(), ++ConstMI->getIterator(), DL,  in INITIALIZE_PASS_DEPENDENCY()
177                               TII->get(IsRow ? X86::MOV8mi : X86::MOV16mi)),  in INITIALIZE_PASS_DEPENDENCY()
184           unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R));  in INITIALIZE_PASS_DEPENDENCY()
190             Iter = ConstMI->getIterator();  in INITIALIZE_PASS_DEPENDENCY()
193                               TII->get(IsRow ? X86::MOV8mr : X86::MOV16mr)),  in INITIALIZE_PASS_DEPENDENCY()
195                       .addReg(R, 0, SubIdx);  in INITIALIZE_PASS_DEPENDENCY()
197           LIS.extendToIndices(LIS.getInterval(R), {SIdx.getRegSlot()});  in INITIALIZE_PASS_DEPENDENCY()