1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
59 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
64     EnableTileRAPass("x86-tile-ra",
65                      cl::desc("Enable the tile register allocation pass"),
133     Ret += "-p:32:32";  in computeDataLayout()
136   Ret += "-p270:32:32-p271:32:32-p272:64:64";  in computeDataLayout()
139   // 128 bit integers are not specified in the 32-bit ABIs but are used  in computeDataLayout()
142     Ret += "-i64:64-i128:128";  in computeDataLayout()
144     Ret += "-i64:32-f64:32";  in computeDataLayout()
146     Ret += "-i128:128-f64:32:64";  in computeDataLayout()
152     Ret += "-f80:128";  in computeDataLayout()
154     Ret += "-f80:32";  in computeDataLayout()
157     Ret += "-f128:32";  in computeDataLayout()
159   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.  in computeDataLayout()
161     Ret += "-n8:16:32:64";  in computeDataLayout()
163     Ret += "-n8:16:32";  in computeDataLayout()
167     Ret += "-a:0:32-S32";  in computeDataLayout()
169     Ret += "-S128";  in computeDataLayout()
183     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.  in getEffectiveRelocModel()
184     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we  in getEffectiveRelocModel()
196   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC  in getEffectiveRelocModel()
198   // executables but not necessarily a shared library. On X86-32 we just  in getEffectiveRelocModel()
199   // compile in -static mode, in x86-64 we use PIC.  in getEffectiveRelocModel()
207   // If we are on Darwin, disallow static relocation model in X86-64 mode, since  in getEffectiveRelocModel()
208   // the Mach-O file format doesn't support it.  in getEffectiveRelocModel()
246     this->Options.TrapUnreachable = true;  in X86TargetMachine()
247     this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();  in X86TargetMachine()
262   Attribute CPUAttr = F.getFnAttribute("target-cpu");  in getSubtargetImpl()
263   Attribute TuneAttr = F.getFnAttribute("tune-cpu");  in getSubtargetImpl()
264   Attribute FSAttr = F.getFnAttribute("target-features");  in getSubtargetImpl()
268   // "x86-64" is a default target setting for many front ends. In these cases,  in getSubtargetImpl()
269   // they actually request for "generic" tuning unless the "tune-cpu" was  in getSubtargetImpl()
272                       : CPU == "x86-64"  ? "generic"  in getSubtargetImpl()
283   // Extract prefer-vector-width attribute.  in getSubtargetImpl()
285   Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");  in getSubtargetImpl()
290       Key += 'p';  in getSubtargetImpl()
296   // Extract min-legal-vector-width attribute.  in getSubtargetImpl()
298   Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");  in getSubtargetImpl()
323   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();  in getSubtargetImpl()
327     Key += FS.empty() ? "+soft-float" : "+soft-float,";  in getSubtargetImpl()
331   // We may have added +soft-float to the features so move the StringRef to  in getSubtargetImpl()
343         MaybeAlign(F.getParent()->getOverrideStackAlignment()),  in getSubtargetImpl()
363   PFS.MF.getInfo<X86MachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);  in parseMachineFunctionInfo()
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
384 //===----------------------------------------------------------------------===//
386 //===----------------------------------------------------------------------===//
403     DAG->addMutation(createX86MacroFusionDAGMutation());  in createMachineScheduler()
410     DAG->addMutation(createX86MacroFusionDAGMutation());  in createPostMachineScheduler()
446 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
449 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",  in INITIALIZE_PASS_DEPENDENCY()
473   if (TM->getOptLevel() != CodeGenOptLevel::None) {  in addIRPasses()
479   // thunk. These will be a no-op unless a function subtarget has the retpoline  in addIRPasses()
484   const Triple &TT = TM->getTargetTriple();  in addIRPasses()
493   if (TM->Options.JMCInstrument)  in addIRPasses()
501   // For ELF, cleanup any local-dynamic TLS accesses.  in addInstSelector()
502   if (TM->getTargetTriple().isOSBinFormatELF() &&  in addInstSelector()
543   // Only add this pass for 32-bit x86 Windows.  in addPreISel()
544   const Triple &TT = TM->getTargetTriple();  in addPreISel()
578   // When -O0 is enabled, the Load Value Injection Hardening pass will fall back  in addPostRegAlloc()
581   // analyses needed by the LVIHardening pass when compiling at -O0.  in addPostRegAlloc()
615   const Triple &TT = TM->getTargetTriple();  in addPreEmitPass2()
616   const MCAsmInfo *MAI = TM->getMCAsmInfo();  in addPreEmitPass2()
641        MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI))  in addPreEmitPass2()
662     return M->getModuleFlag("kcfi") ||  in addPreEmitPass2()
664             (M->getFunction("objc_retainAutoreleasedReturnValue") ||  in addPreEmitPass2()
665              M->getFunction("objc_unsafeClaimAutoreleasedReturnValue")));  in addPreEmitPass2()
675   return getStandardCSEConfigForOpt(TM->getOptLevel());  in getCSEConfig()
686   // Don't support tile RA when RA is specified by command line "-regalloc".  in addRegAssignAndRewriteOptimized()
688     // Allocate tile register first.  in addRegAssignAndRewriteOptimized()