Lines Matching +full:entry +full:- +full:latency
1 //=- X86ScheduleZnver2.td - X86 Znver2 Scheduling -------------*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
33 // Zen can issue micro-ops to 10 different units in one cycle.
67 // Micro-ops to be issued to multiple units are tackled this way.
70 // Zn2ALU03 - 0,3 grouping
73 // 64 Entry (16x4 entries) Int Scheduler
78 // 28 Entry (14x2) AGU group. AGUs can't be used for all ALU operations
90 // 4 Cycles load-to use Latency is captured
93 // 7 Cycles vector load-to use Latency is captured
101 // speculative version of the 64-bit integer registers.
105 // 36 Entry (9x4 entries) floating-point Scheduler
110 // The Zen FP Retire Queue renames SIMD and FP uOps onto a pool of 160 128-bit
111 // registers. Operations on 256-bit data types are cracked into two COPs.
115 // The unit can track up to 192 macro ops in-flight.
116 // The retire unit handles in-order commit of up to 8 macro ops per cycle.
119 // In SMT mode it is 96 entry per thread. But, we do not use the conservative
125 // Ex: ADDPD xmm,[mem]-> This instruction has two micro-ops
126 // Instructions with folded loads are usually micro-fused, so they only appear
127 // as two micro-ops.
135 // Register variant takes 1-cycle on Execution Port.
137 let Latency = Lat;
143 // adds LoadLat cycles to the latency (default = 4).
145 let Latency = !add(Lat, LoadLat);
156 // Register variant takes 1-cycle on Execution Port.
158 let Latency = Lat;
164 // adds LoadLat cycles to the latency (default = 7).
166 let Latency = !add(Lat, LoadLat);
179 def : WriteRes<WriteLoad, [Zn2AGU]> { let Latency = 4; }
181 // Model the effect of clobbering the read-write mask operand of the GATHER operation.
182 // Does not cost anything by itself, only has latency, matching that of the WriteLoad,
183 def : WriteRes<WriteVecMaskedGatherWriteback, []> { let Latency = 8; let NumMicroOps = 0; }
248 let Latency = 3;
252 let Latency = !add(Zn2WriteIMulH.Latency, Znver2Model.LoadLatency);
456 let Latency = 2;
460 let Latency = 5;
472 let Latency = 2;
486 let Latency = 100;
511 // - r: register.
512 // - m = memory.
513 // - i = immediate
514 // - mm: 64 bit mmx register.
515 // - x = 128 bit xmm register.
516 // - (x)mm = mmx or xmm register.
517 // - y = 256 bit ymm register.
518 // - v = any vector register.
521 //-- Move instructions --//
536 let Latency = 5;
546 let Latency = 5;
558 let Latency = 4;
567 let Latency = 8;
577 let Latency = 5;
584 //-- Arithmetic instructions --//
607 let Latency = 3;
610 let Latency = 4;
618 let Latency = 7;
626 let Latency = 3;
634 let Latency = 7;
642 let Latency = 4;
651 let Latency = 8;
659 // Numbers are based on the AMD SOG for Family 17h - Instruction Latencies.
663 //-- Control transfer instructions --//
691 //-- Logic instructions --//
699 // Define ALU latency variants
701 let Latency = 2;
704 let Latency = 6;
710 let Latency = 6;
741 //-- Misc instructions --//
752 let Latency = 8;
766 //-- Move instructions --//
771 let Latency = 5;
791 let Latency = 5;
802 let Latency = 11;
809 let Latency = 12;
814 let Latency = 8;
818 let Latency = 11;
846 //-- Arithmetic instructions --//
853 let Latency = 8;
871 let Latency = 9;
880 let Latency = 12;
904 let Latency = 8;
922 let Latency = 8;
927 let Latency = 9;
949 let Latency = 8;
958 let Latency = 8;
968 //-- Arithmetic instructions --//
982 // x <- x,m.
984 let Latency = 8;
988 let Latency = 8;
994 //-- Move instructions --//
1004 let Latency = 8;
1013 let Latency = 2;
1020 let Latency = 5;
1037 let Latency = 2;
1041 let Latency = 9;
1054 //-- Conversion instructions --//
1056 let Latency = 3;
1059 let Latency = 3;
1071 let Latency = 10;
1078 let Latency = 10;
1095 let Latency = 3;
1102 let Latency = 10;
1111 let Latency = 3;
1119 let Latency = 3;
1125 let Latency = 10;
1132 let Latency = 3;
1144 let Latency = 3;
1151 let Latency = 10;
1163 let Latency = 4;
1178 let Latency = 3;
1190 let Latency = 3;
1198 let Latency = 4;
1201 let Latency = 11;
1229 //-- SSE4A instructions --//
1232 let Latency = 3;
1238 let Latency = 4;
1242 //-- SHA instructions --//
1249 let Latency = 2;
1254 let Latency = 9;
1264 let Latency = 8;
1274 let Latency = 8;
1281 let Latency = 6;
1286 let Latency = 13;
1293 let Latency = 4;
1298 let Latency = 11;
1302 //-- Arithmetic instructions --//
1319 //-- Other instructions --//
1329 // GPR Zero-idioms.
1335 // MMX Zero-idioms.
1343 // SSE Zero-idioms.
1354 // AVX XMM Zero-idioms.
1365 // AVX YMM Zero-idioms.