Lines Matching +full:64 +full:m
73 // 64 Entry (16x4 entries) Int Scheduler
75 let BufferSize=64;
101 // speculative version of the 64-bit integer registers.
512 // - m = memory.
514 // - mm: 64 bit mmx register.
523 // r16,m.
532 def : InstRW<[Zn2WriteXCHG], (instregex "^XCHG(8|16|32|64)rr", "^XCHG(16|32|64)ar")>;
534 // r,m.
539 def : InstRW<[Zn2WriteXCHGrm, ReadAfterLd], (instregex "^XCHG(8|16|32|64)rm")>;
556 // m.
575 // r,m.
579 def : InstRW<[Zn2WriteMOVBE, ReadAfterLd], (instregex "MOVBE(16|32|64)rm")>;
582 def : InstRW<[Zn2WriteMOVBE], (instregex "MOVBE(16|32|64)mr")>;
587 // m,r/i.
588 def : InstRW<[WriteALULd], (instregex "(ADD|SUB)(8|16|32|64)m(r|i)",
589 "(ADD|SUB)(8|16|32|64)mi8",
590 "(ADD|SUB)64mi32")>;
593 // m,r/i.
595 (instregex "(ADC|SBB)(8|16|32|64)m(r|i)",
596 "(ADC|SBB)(16|32|64)mi8",
597 "(ADC|SBB)64mi32")>;
600 // m.
602 (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m")>;
682 def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>;
688 def : InstRW<[Zn2WriteRET], (instregex "RET(16|32|64)", "LRET(16|32|64)",
689 "IRET(16|32|64)")>;
694 // m,r/i.
696 (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
697 "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>;
708 // m,r,i.
713 // m,r,i.
719 def : InstRW<[WriteMicrocoded], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>;
720 // r,r,m.
721 def : InstRW<[WriteMicrocoded], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>;
724 // m,i.
725 def : InstRW<[WriteMicrocoded], (instregex "RC(R|L)(8|16|32|64)m(1|i|CL)")>;
728 // m,i.
729 def : InstRW<[WriteShiftLd], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>;
732 // m,r
733 def : InstRW<[WriteShiftLd], (instregex "SH(R|L)D(16|32|64)mri8")>;
736 def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)rrCL")>;
738 // m,r,cl.
739 def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)mrCL")>;
762 def : InstRW<[Zn2XADD], (instregex "XADD(8|16|32|64)rr")>;
763 def : InstRW<[WriteMicrocoded], (instregex "XADD(8|16|32|64)rm")>;
779 // m.
805 def : InstRW<[Zn2WriteFILD], (instregex "ILD_F(16|32|64)m")>;
811 def : InstRW<[Zn2WriteFIST], (instregex "IS(T|TT)_(F|FP)(16|32|64)m")>;
862 // m.
863 def : InstRW<[Zn2WriteFPU0Lat1Ld], (instregex "FCOM(P?)(32|64)m")>;
875 // m.
886 def : InstRW<[Zn2WriteFPU03], (instregex "FICOM(P?)(16|32)m")>;
919 // v,v,m,i
934 def : InstRW<[WriteMicrocoded], (instregex "MMX_MASKMOVQ(64)?")>;
937 def : InstRW<[WriteMicrocoded], (instregex "(V?)MASKMOVDQU(64)?")>;
943 // m, v,v.
982 // x <- x,m.
1184 def : InstRW<[Zn2WriteCVTPD2DQr], (instregex "(V?)CVT(T?)SS2SI(64)?rr")>;
1187 def : InstRW<[Zn2WriteCVTPD2DQLd], (instregex "(V?)CVT(T?)SS2SI(64)?rm")>;
1193 // x,r32/64.
1194 def : InstRW<[Zn2WriteCVSTSI2SDr], (instregex "(V?)CVTSI(64)?2SDrr")>;
1204 // r32/64
1205 def : InstRW<[Zn2WriteCVSTSI2SIr], (instregex "(V?)CVT(T?)SD2SI(64)?rr")>;
1207 def : InstRW<[Zn2WriteCVSTSI2SILd], (instregex "(V?)CVT(T?)SD2SI(64)?rm")>;
1214 // m,v,i.
1224 // v,m.
1244 def : InstRW<[WriteMicrocoded], (instregex "SHA256MSG2(Y?)r(r|m)")>;
1252 // x,m.
1262 // x,m.
1272 // x,m.
1284 // x,m.
1296 // x,m.
1309 // x,m,i / v,v,m,i.
1316 // x,m,i.