Lines Matching +full:entry +full:- +full:latency
1 //=- X86ScheduleZnver1.td - X86 Znver1 Scheduling -------------*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
33 // Zen can issue micro-ops to 10 different units in one cycle.
66 // Micro-ops to be issued to multiple units are tackled this way.
69 // ZnALU03 - 0,3 grouping
72 // 56 Entry (14x4 entries) Int Scheduler
77 // 28 Entry (14x2) AGU group. AGUs can't be used for all ALU operations
89 // 4 Cycles integer load-to use Latency is captured
92 // 8 Cycles vector load-to use Latency is captured
100 // speculative version of the 64-bit integer registers.
104 // 36 Entry (9x4 entries) floating-point Scheduler
109 // The Zen FP Retire Queue renames SIMD and FP uOps onto a pool of 160 128-bit
110 // registers. Operations on 256-bit data types are cracked into two COPs.
114 // The unit can track up to 192 macro ops in-flight.
115 // The retire unit handles in-order commit of up to 8 macro ops per cycle.
118 // In SMT mode it is 96 entry per thread. But, we do not use the conservative
126 // Ex: ADDPD xmm,[mem]-> This instruction has two micro-ops
127 // Instructions with folded loads are usually micro-fused, so they only appear
128 // as two micro-ops.
136 // Register variant takes 1-cycle on Execution Port.
138 let Latency = Lat;
144 // adds LoadLat cycles to the latency (default = 4).
146 let Latency = !add(Lat, LoadLat);
157 // Register variant takes 1-cycle on Execution Port.
159 let Latency = Lat;
165 // adds LoadLat cycles to the latency (default = 7).
167 let Latency = !add(Lat, LoadLat);
180 def : WriteRes<WriteLoad, [ZnAGU]> { let Latency = 4; }
182 // Model the effect of clobbering the read-write mask operand of the GATHER operation.
183 // Does not cost anything by itself, only has latency, matching that of the WriteLoad,
184 def : WriteRes<WriteVecMaskedGatherWriteback, []> { let Latency = 8; let NumMicroOps = 0; }
249 let Latency = 3;
253 let Latency = !add(ZnWriteIMulH.Latency, Znver1Model.LoadLatency);
457 let Latency = 2;
461 let Latency = 5;
473 let Latency = 2;
487 let Latency = 100;
512 // - r: register.
513 // - m = memory.
514 // - i = immediate
515 // - mm: 64 bit mmx register.
516 // - x = 128 bit xmm register.
517 // - (x)mm = mmx or xmm register.
518 // - y = 256 bit ymm register.
519 // - v = any vector register.
522 //-- Move instructions --//
530 let Latency = 5;
540 let Latency = 5;
552 let Latency = 4;
561 let Latency = 8;
571 let Latency = 5;
578 //-- Arithmetic instructions --//
601 let Latency = 3;
609 let Latency = 8;
616 let Latency = 3;
624 let Latency = 8;
632 let Latency = 4;
641 let Latency = 9;
649 // Numbers are based on the AMD SOG for Family 17h - Instruction Latencies.
653 //-- Control transfer instructions --//
681 //-- Logic instructions --//
689 // Define ALU latency variants
691 let Latency = 2;
694 let Latency = 6;
700 let Latency = 6;
731 //-- Misc instructions --//
742 let Latency = 8;
756 //-- Move instructions --//
761 let Latency = 5;
781 let Latency = 5;
792 let Latency = 11;
799 let Latency = 12;
804 let Latency = 8;
808 let Latency = 11;
836 //-- Arithmetic instructions --//
843 let Latency = 8;
861 let Latency = 9;
870 let Latency = 12;
894 let Latency = 8;
912 let Latency = 8;
917 let Latency = 9;
939 let Latency = 8;
948 let Latency = 8;
958 //-- Arithmetic instructions --//
972 // x <- x,m.
974 let Latency = 8;
978 let Latency = 8;
986 //-- Move instructions --//
996 let Latency = 8;
1005 let Latency = 2;
1012 let Latency = 5;
1029 let Latency = 2;
1033 let Latency = 9;
1047 //-- Conversion instructions --//
1049 let Latency = 4;
1052 let Latency = 5;
1066 let Latency = 11;
1073 let Latency = 11;
1092 let Latency = 3;
1099 let Latency = 10;
1108 let Latency = 3;
1116 let Latency = 4;
1122 let Latency = 11;
1129 let Latency = 5;
1140 let Latency = 5;
1147 let Latency = 12;
1159 let Latency = 4;
1174 let Latency = 5;
1186 let Latency = 5;
1194 let Latency = 5;
1197 let Latency = 12;
1225 //-- SSE4A instructions --//
1228 let Latency = 2;
1234 let Latency = 4;
1238 //-- SHA instructions --//
1245 let Latency = 2;
1251 let Latency = 9;
1262 let Latency = 8;
1272 let Latency = 8;
1279 let Latency = 6;
1284 let Latency = 13;
1291 let Latency = 4;
1296 let Latency = 11;
1300 //-- Arithmetic instructions --//
1323 // GPR Zero-idioms.
1329 // MMX Zero-idioms.
1337 // SSE Zero-idioms.
1348 // AVX XMM Zero-idioms.
1359 // AVX YMM Zero-idioms.