Lines Matching +full:7 +full:z
39 // stores. Port 7 can handle address calculations.
77 // Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
78 // until 5/6/7 cycles after the memory operand.
81 def : ReadAdvance<ReadAfterVecYLd, 7>;
111 // 2/3/7 cycle to recompute the address.
146 …iteDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
147 …iteDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
148 …iteDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>;
229 defm : X86WriteRes<WriteFLoadY, [SKXPort23], 7, [1], 1>;
230 defm : X86WriteRes<WriteFMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>;
252 defm : SKXWriteResPair<WriteFAddY, [SKXPort01], 4, [1], 1, 7>;
253 defm : SKXWriteResPair<WriteFAddZ, [SKXPort05], 4, [1], 1, 7>;
256 defm : SKXWriteResPair<WriteFAdd64Y, [SKXPort01], 4, [1], 1, 7>;
257 defm : SKXWriteResPair<WriteFAdd64Z, [SKXPort05], 4, [1], 1, 7>;
261 defm : SKXWriteResPair<WriteFCmpY, [SKXPort01], 4, [1], 1, 7>;
262 defm : SKXWriteResPair<WriteFCmpZ, [SKXPort05], 4, [1], 1, 7>;
265 defm : SKXWriteResPair<WriteFCmp64Y, [SKXPort01], 4, [1], 1, 7>;
266 defm : SKXWriteResPair<WriteFCmp64Z, [SKXPort05], 4, [1], 1, 7>;
273 defm : SKXWriteResPair<WriteFMulY, [SKXPort01], 4, [1], 1, 7>;
274 defm : SKXWriteResPair<WriteFMulZ, [SKXPort05], 4, [1], 1, 7>;
277 defm : SKXWriteResPair<WriteFMul64Y, [SKXPort01], 4, [1], 1, 7>;
278 defm : SKXWriteResPair<WriteFMul64Z, [SKXPort05], 4, [1], 1, 7>;
282 defm : SKXWriteResPair<WriteFDivY, [SKXPort0,SKXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles.
283 defm : SKXWriteResPair<WriteFDivZ, [SKXPort0,SKXPort5,SKXFPDivider], 18, [2,1,10], 3, 7>; // 10-…
286 defm : SKXWriteResPair<WriteFDiv64Y, [SKXPort0,SKXFPDivider], 14, [1,8], 1, 7>; // 10-14 cycles.
287 defm : SKXWriteResPair<WriteFDiv64Z, [SKXPort0,SKXPort5,SKXFPDivider], 23, [2,1,16], 3, 7>; // 10-…
291 defm : SKXWriteResPair<WriteFSqrtY, [SKXPort0,SKXFPDivider], 12, [1,6], 1, 7>;
292 defm : SKXWriteResPair<WriteFSqrtZ, [SKXPort0,SKXPort5,SKXFPDivider], 20, [2,1,12], 3, 7>;
295 defm : SKXWriteResPair<WriteFSqrt64Y, [SKXPort0,SKXFPDivider], 18, [1,12],1, 7>;
296 defm : SKXWriteResPair<WriteFSqrt64Z, [SKXPort0,SKXPort5,SKXFPDivider], 32, [2,1,24], 3, 7>;
297 defm : SKXWriteResPair<WriteFSqrt80, [SKXPort0,SKXFPDivider], 21, [1,7]>; // Floating point long d…
301 defm : SKXWriteResPair<WriteFRcpY, [SKXPort0], 4, [1], 1, 7>;
302 defm : SKXWriteResPair<WriteFRcpZ, [SKXPort0,SKXPort5], 4, [2,1], 3, 7>;
306 defm : SKXWriteResPair<WriteFRsqrtY,[SKXPort0], 4, [1], 1, 7>;
307 defm : SKXWriteResPair<WriteFRsqrtZ,[SKXPort0,SKXPort5], 9, [2,1], 3, 7>;
311 defm : SKXWriteResPair<WriteFMAY, [SKXPort01], 4, [1], 1, 7>;
312 defm : SKXWriteResPair<WriteFMAZ, [SKXPort05], 4, [1], 1, 7>;
320 defm : SKXWriteResPair<WriteFRndY, [SKXPort01], 8, [2], 2, 7>;
321 defm : SKXWriteResPair<WriteFRndZ, [SKXPort05], 8, [2], 2, 7>;
323 defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>;
324 defm : SKXWriteResPair<WriteFLogicZ, [SKXPort05], 1, [1], 1, 7>;
326 defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>;
327 defm : SKXWriteResPair<WriteFTestZ, [SKXPort0], 2, [1], 1, 7>;
329 defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>;
330 defm : SKXWriteResPair<WriteFShuffleZ, [SKXPort5], 1, [1], 1, 7>;
332 defm : SKXWriteResPair<WriteFVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
333 defm : SKXWriteResPair<WriteFVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
335 defm : SKXWriteResPair<WriteFBlendY,[SKXPort015], 1, [1], 1, 7>;
336 defm : SKXWriteResPair<WriteFBlendZ,[SKXPort015], 1, [1], 1, 7>;
338 defm : SKXWriteResPair<WriteFVarBlendY,[SKXPort015], 2, [2], 2, 7>;
339 defm : SKXWriteResPair<WriteFVarBlendZ,[SKXPort015], 2, [2], 2, 7>;
347 defm : X86WriteRes<WriteVecLoadY, [SKXPort23], 7, [1], 1>;
349 defm : X86WriteRes<WriteVecLoadNTY, [SKXPort23], 7, [1], 1>;
350 defm : X86WriteRes<WriteVecMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>;
370 defm : SKXWriteResPair<WriteVecALUY, [SKXPort01], 1, [1], 1, 7>;
371 defm : SKXWriteResPair<WriteVecALUZ, [SKXPort0], 1, [1], 1, 7>;
374 defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>;
375 defm : SKXWriteResPair<WriteVecLogicZ,[SKXPort05], 1, [1], 1, 7>;
377 defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
378 defm : SKXWriteResPair<WriteVecTestZ, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
381 defm : SKXWriteResPair<WriteVecIMulY, [SKXPort01], 5, [1], 1, 7>;
382 defm : SKXWriteResPair<WriteVecIMulZ, [SKXPort05], 5, [1], 1, 7>;
384 defm : SKXWriteResPair<WritePMULLDY, [SKXPort01], 10, [2], 2, 7>;
385 defm : SKXWriteResPair<WritePMULLDZ, [SKXPort05], 10, [2], 2, 7>;
388 defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>;
389 defm : SKXWriteResPair<WriteShuffleZ, [SKXPort5], 1, [1], 1, 7>;
392 defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
393 defm : SKXWriteResPair<WriteVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
395 defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>;
396 defm : SKXWriteResPair<WriteBlendZ,[SKXPort5], 1, [1], 1, 7>;
401 defm : SKXWriteResPair<WriteMPSADY, [SKXPort5], 4, [2], 2, 7>;
402 defm : SKXWriteResPair<WriteMPSADZ, [SKXPort5], 4, [2], 2, 7>;
405 defm : SKXWriteResPair<WritePSADBWY, [SKXPort5], 3, [1], 1, 7>;
406 defm : SKXWriteResPair<WritePSADBWZ, [SKXPort5], 3, [1], 1, 7>; // TODO: 512-bit ops require ports …
414 defm : X86WriteRes<WriteVecShiftXLd, [SKXPort01,SKXPort23], 7, [1,1], 2>;
420 defm : SKXWriteResPair<WriteVecShiftImmY, [SKXPort01], 1, [1], 1, 7>;
421 defm : SKXWriteResPair<WriteVecShiftImmZ, [SKXPort0], 1, [1], 1, 7>;
423 defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>;
424 defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>;
472 defm : SKXWriteResPair<WriteCvtPD2PSY, [SKXPort5,SKXPort01], 7, [1,1], 2, 7>;
473 defm : SKXWriteResPair<WriteCvtPD2PSZ, [SKXPort5,SKXPort05], 7, [1,1], 2, 7>;
476 defm : X86WriteRes<WriteCvtPH2PSY, [SKXPort5,SKXPort01], 7, [1,1], 2>;
477 defm : X86WriteRes<WriteCvtPH2PSZ, [SKXPort5,SKXPort0], 7, [1,1], 2>;
483 defm : X86WriteRes<WriteCvtPS2PHY, [SKXPort5,SKXPort01], 7, [1,1], 2>;
484 defm : X86WriteRes<WriteCvtPS2PHZ, [SKXPort5,SKXPort05], 7, [1,1], 2>;
595 defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuf…
596 defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector v…
597 defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector shuffle…
598 defm : SKXWriteResPair<WriteVPMOV256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width packed vector wi…
599 defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector vari…
608 def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps =…
619 defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort01], 6, [2,1], 3, 7>;
622 defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>;
649 "VPMOVB2M(Z|Z128|Z256)rr",
650 "VPMOVD2M(Z|Z128|Z256)rr",
651 "VPMOVQ2M(Z|Z128|Z256)rr",
652 "VPMOVW2M(Z|Z128|Z256)rr")>;
698 "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr",
705 "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk",
706 "VPTERNLOGD(Z|Z128|Z256)rri",
707 "VPTERNLOGQ(Z|Z128|Z256)rri")>;
832 "VALIGND(Z|Z128|Z256)rri",
833 "VALIGNQ(Z|Z128|Z256)rri",
835 "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr")>;
846 "VCMPPD(Z|Z128|Z256)rri",
847 "VCMPPS(Z|Z128|Z256)rri",
849 "VFPCLASS(PD|PS)(Z|Z128|Z256)rr",
851 "VPCMPB(Z|Z128|Z256)rri",
852 "VPCMPD(Z|Z128|Z256)rri",
853 "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",
854 "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr",
855 "VPCMPQ(Z|Z128|Z256)rri",
856 "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri",
857 "VPCMPW(Z|Z128|Z256)rri",
858 "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>;
989 def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
990 "VEXPANDPS(Z|Z128|Z256)rr",
991 "VPEXPANDD(Z|Z128|Z256)rr",
992 "VPEXPANDQ(Z|Z128|Z256)rr",
993 "VPMOVDB(Z|Z128|Z256)rr",
994 "VPMOVDW(Z|Z128|Z256)rr",
995 "VPMOVQB(Z|Z128|Z256)rr",
996 "VPMOVQW(Z|Z128|Z256)rr",
997 "VPMOVSDB(Z|Z128|Z256)rr",
998 "VPMOVSDW(Z|Z128|Z256)rr",
999 "VPMOVSQB(Z|Z128|Z256)rr",
1000 "VPMOVSQD(Z|Z128|Z256)rr",
1001 "VPMOVSQW(Z|Z128|Z256)rr",
1002 "VPMOVSWB(Z|Z128|Z256)rr",
1003 "VPMOVUSDB(Z|Z128|Z256)rr",
1004 "VPMOVUSDW(Z|Z128|Z256)rr",
1005 "VPMOVUSQB(Z|Z128|Z256)rr",
1006 "VPMOVUSQD(Z|Z128|Z256)rr",
1007 "VPMOVUSWB(Z|Z128|Z256)rr",
1008 "VPMOVWB(Z|Z128|Z256)rr")>;
1017 "VPMOVQD(Z|Z128|Z256)mr(b?)")>;
1099 def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
1100 "VPMOVDW(Z|Z128|Z256)mr(b?)",
1101 "VPMOVQB(Z|Z128|Z256)mr(b?)",
1102 "VPMOVQW(Z|Z128|Z256)mr(b?)",
1103 "VPMOVSDB(Z|Z128|Z256)mr(b?)",
1104 "VPMOVSDW(Z|Z128|Z256)mr(b?)",
1105 "VPMOVSQB(Z|Z128|Z256)mr(b?)",
1106 "VPMOVSQD(Z|Z128|Z256)mr(b?)",
1107 "VPMOVSQW(Z|Z128|Z256)mr(b?)",
1108 "VPMOVSWB(Z|Z128|Z256)mr(b?)",
1109 "VPMOVUSDB(Z|Z128|Z256)mr(b?)",
1110 "VPMOVUSDW(Z|Z128|Z256)mr(b?)",
1111 "VPMOVUSQB(Z|Z128|Z256)mr(b?)",
1112 "VPMOVUSQD(Z|Z128|Z256)mr(b?)",
1113 "VPMOVUSQW(Z|Z128|Z256)mr(b?)",
1114 "VPMOVUSWB(Z|Z128|Z256)mr(b?)",
1115 "VPMOVWB(Z|Z128|Z256)mr(b?)")>;
1149 def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
1150 "VCOMPRESSPS(Z|Z128|Z256)rr",
1151 "VPCOMPRESSD(Z|Z128|Z256)rr",
1152 "VPCOMPRESSQ(Z|Z128|Z256)rr",
1153 "VPERMW(Z|Z128|Z256)rr")>;
1254 let Latency = 7;
1270 let Latency = 7;
1277 let Latency = 7;
1297 let Latency = 7;
1316 let Latency = 7;
1335 let Latency = 7;
1371 let Latency = 7;
1380 let Latency = 7;
1392 let Latency = 7;
1400 let Latency = 7;
1404 def: InstRW<[SKXWriteResGroup100], (instregex "(V?)CVT(T?)SS2SI64(Z?)rr",
1408 let Latency = 7;
1415 let Latency = 7;
1422 let Latency = 7;
1429 let Latency = 7;
1433 def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
1434 "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
1435 "VPCOMPRESSD(Z|Z128|Z256)mr(b?)",
1436 "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>;
1439 let Latency = 7;
1455 let Latency = 7;
1462 let Latency = 7;
1470 let Latency = 7;
1471 let NumMicroOps = 7;
1480 let Latency = 7;
1481 let NumMicroOps = 7;
1487 let Latency = 7;
1497 let Latency = 7;
1509 let Latency = 7;
1529 "VPBROADCASTB(Z|Z256)rm(b?)",
1530 "VPBROADCASTW(Z|Z256)rm(b?)")>;
1545 (instregex "VBLENDMPD(Z|Z256)rm(b?)",
1546 "VBLENDMPS(Z|Z256)rm(b?)",
1563 "VBROADCASTSD(Z|Z256)rm(b?)",
1564 "VBROADCASTSS(Z|Z256)rm(b?)",
1565 "VINSERTF32x4(Z|Z256)rm(b?)",
1567 "VINSERTF64x2(Z|Z256)rm(b?)",
1569 "VINSERTI32x4(Z|Z256)rm(b?)",
1571 "VINSERTI64x2(Z|Z256)rm(b?)",
1573 "VMOVAPD(Z|Z256)rm(b?)",
1574 "VMOVAPS(Z|Z256)rm(b?)",
1575 "VMOVDDUP(Z|Z256)rm(b?)",
1576 "VMOVDQA32(Z|Z256)rm(b?)",
1577 "VMOVDQA64(Z|Z256)rm(b?)",
1578 "VMOVDQU16(Z|Z256)rm(b?)",
1579 "VMOVDQU32(Z|Z256)rm(b?)",
1580 "VMOVDQU64(Z|Z256)rm(b?)",
1581 "VMOVDQU8(Z|Z256)rm(b?)",
1582 "VMOVSHDUP(Z|Z256)rm(b?)",
1583 "VMOVSLDUP(Z|Z256)rm(b?)",
1584 "VMOVUPD(Z|Z256)rm(b?)",
1585 "VMOVUPS(Z|Z256)rm(b?)",
1587 "VPADD(B|D|Q|W)(Z|Z256)rm(b?)",
1588 "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)",
1589 "VPBROADCASTD(Z|Z256)rm(b?)",
1590 "VPBROADCASTQ(Z|Z256)rm(b?)",
1592 "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)",
1593 "VPTERNLOGD(Z|Z256)rm(b?)i",
1594 "VPTERNLOGQ(Z|Z256)rm(b?)i")>;
1752 "VALIGND(Z|Z256)rm(b?)i",
1753 "VALIGNQ(Z|Z256)rm(b?)i",
1754 "VPMAXSQ(Z|Z256)rm(b?)",
1755 "VPMAXUQ(Z|Z256)rm(b?)",
1756 "VPMINSQ(Z|Z256)rm(b?)",
1757 "VPMINUQ(Z|Z256)rm(b?)")>;
1764 def: InstRW<[SKXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i",
1765 "VCMPPS(Z|Z256)rm(b?)i",
1766 "VFPCLASSPD(Z|Z256)rm(b?)",
1767 "VFPCLASSPS(Z|Z256)rm(b?)",
1768 "VPCMPB(Z|Z256)rmi(b?)",
1769 "VPCMPD(Z|Z256)rmi(b?)",
1770 "VPCMPEQB(Z|Z256)rm(b?)",
1771 "VPCMPEQD(Z|Z256)rm(b?)",
1772 "VPCMPEQQ(Z|Z256)rm(b?)",
1773 "VPCMPEQW(Z|Z256)rm(b?)",
1774 "VPCMPGTB(Z|Z256)rm(b?)",
1775 "VPCMPGTD(Z|Z256)rm(b?)",
1776 "VPCMPGTQ(Z|Z256)rm(b?)",
1777 "VPCMPGTW(Z|Z256)rm(b?)",
1778 "VPCMPQ(Z|Z256)rmi(b?)",
1781 "VPCMPW(Z|Z256)rmi(b?)",
1859 def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)",
1860 "VCVTPH2PS(Z|Z256)rm(b?)",
1861 "VCVTPS2PD(Z|Z256)rm(b?)",
1862 "VCVTQQ2PD(Z|Z256)rm(b?)",
1864 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",
1865 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",
1867 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",
1869 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",
1871 "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)",
1872 "VCVTUQQ2PD(Z|Z256)rm(b?)",
1881 "VEXPANDPD(Z|Z256)rm(b?)",
1882 "VEXPANDPS(Z|Z256)rm(b?)",
1883 "VPEXPANDD(Z|Z256)rm(b?)",
1884 "VPEXPANDQ(Z|Z256)rm(b?)")>;
1912 let NumMicroOps = 7;
2159 let ReleaseAtCycles = [1,2,7];
2258 let ReleaseAtCycles = [9,7,5];
2302 let ReleaseAtCycles = [9,7,1,5];
2331 let ReleaseAtCycles = [17,11,7];
2338 let ReleaseAtCycles = [17,11,1,7];
2480 // CMOVs that use both Z and C flag require an extra uop.
2488 let Latency = 7;
2506 // SETCCs that use both Z and C flag require an extra uop.