Lines Matching refs:BasePtr
70 BasePtr = Use64BitReg ? X86::RBX : X86::EBX; in X86RegisterInfo()
75 BasePtr = X86::ESI; in X86RegisterInfo()
575 Register BasePtr = getX86SubSuperRegister(getBaseRegister(), 64); in getReservedRegs() local
576 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr)) in getReservedRegs()
793 return MRI->canReserveReg(BasePtr); in canRealignStack()
818 Register BasePtr = MI.getOperand(1).getReg(); in tryOptimizeLEAtoMOV() local
823 BasePtr = getX86SubSuperRegister(BasePtr, 32); in tryOptimizeLEAtoMOV()
827 TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr, in tryOptimizeLEAtoMOV()
861 assert(BasePtr == FramePtr && "Expected the FP as base register"); in eliminateFrameIndex()
898 Register BasePtr; in eliminateFrameIndex() local
904 TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0).getFixed(); in eliminateFrameIndex()
906 FIOffset = TFI->getWin64EHFrameIndexRef(MF, FrameIndex, BasePtr); in eliminateFrameIndex()
908 FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed(); in eliminateFrameIndex()
927 Register MachineBasePtr = BasePtr; in eliminateFrameIndex()
928 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr)) in eliminateFrameIndex()
929 MachineBasePtr = getX86SubSuperRegister(BasePtr, 64); in eliminateFrameIndex()
935 if (BasePtr == StackPtr) in eliminateFrameIndex()
941 assert(BasePtr == FramePtr && "Expected the FP as base register"); in eliminateFrameIndex()