Lines Matching +full:super +full:- +full:set
1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
45 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
59 // Use a callee-saved register as the base pointer. These registers must in X86RegisterInfo()
60 // not conflict with any ABI requirements. For example, in 32-bit mode PIC in X86RegisterInfo()
64 // This matches the simplified 32-bit pointer code in the data layout in X86RegisterInfo()
87 // The sub_8bit sub-register index is more constrained in 32-bit mode. in getSubClassWithSubReg()
100 // The sub_8bit sub-register index is more constrained in 32-bit mode. in getMatchingSuperRegClass()
112 // Don't allow super-classes of GR8_NOREX. This class is only used after in getLargestLegalSuperClass()
113 // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied in getLargestLegalSuperClass()
114 // to the full GR8 register class in 64-bit mode, so we cannot allow the in getLargestLegalSuperClass()
118 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the in getLargestLegalSuperClass()
125 const TargetRegisterClass *Super = RC; in getLargestLegalSuperClass() local
126 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); in getLargestLegalSuperClass()
128 switch (Super->getID()) { in getLargestLegalSuperClass()
131 // If AVX-512 isn't supported we should only inflate to these classes. in getLargestLegalSuperClass()
133 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
134 return Super; in getLargestLegalSuperClass()
140 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
141 return Super; in getLargestLegalSuperClass()
147 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
148 return Super; in getLargestLegalSuperClass()
152 // If AVX-512 isn't support we shouldn't inflate to these classes. in getLargestLegalSuperClass()
154 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
155 return Super; in getLargestLegalSuperClass()
170 // Don't return a super-class that would shrink the spill size. in getLargestLegalSuperClass()
172 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
173 return Super; in getLargestLegalSuperClass()
175 Super = *I++; in getLargestLegalSuperClass()
176 } while (Super); in getLargestLegalSuperClass()
190 // we can still use 64-bit register as long as we know the high bits in getPointerRegClass()
194 // When the target also allows 64-bit frame pointer and we do have a in getPointerRegClass()
197 return TFI->hasFP(MF) && TFI->Uses64BitFramePtr in getPointerRegClass()
216 case 4: // Available for tailcall (not callee-saved GPRs). in getPointerRegClass()
228 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 && in shouldRewriteCopySrc()
229 SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit) in shouldRewriteCopySrc()
266 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0; in getRegPressureLimit()
267 switch (RC->getID()) { in getRegPressureLimit()
271 return 4 - FPDiff; in getRegPressureLimit()
273 return 12 - FPDiff; in getRegPressureLimit()
285 const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>(); in getCalleeSavedRegs()
286 const Function &F = MF->getFunction(); in getCalleeSavedRegs()
290 bool CallsEHReturn = MF->callsEHReturn(); in getCalleeSavedRegs()
294 // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling in getCalleeSavedRegs()
296 if (MF->getFunction().hasFnAttribute("no_caller_saved_registers")) in getCalleeSavedRegs()
300 // calling convention and use the empty set instead. in getCalleeSavedRegs()
301 if (MF->getFunction().hasFnAttribute("no_callee_saved_registers")) in getCalleeSavedRegs()
323 return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ? in getCalleeSavedRegs()
353 assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86"); in getCalleeSavedRegs()
395 bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() && in getCalleeSavedRegs()
414 if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && in getCalleeSavedRegsViaCopy()
415 MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR()) in getCalleeSavedRegsViaCopy()
475 assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86"); in getCallPreservedMask()
516 bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() && in getCallPreservedMask()
540 // Set the floating point control register as reserved. in getReservedRegs()
541 Reserved.set(X86::FPCW); in getReservedRegs()
543 // Set the floating point status register as reserved. in getReservedRegs()
544 Reserved.set(X86::FPSW); in getReservedRegs()
546 // Set the SIMD floating point control register as reserved. in getReservedRegs()
547 Reserved.set(X86::MXCSR); in getReservedRegs()
549 // Set the stack-pointer register and its aliases as reserved. in getReservedRegs()
551 Reserved.set(SubReg); in getReservedRegs()
553 // Set the Shadow Stack Pointer as reserved. in getReservedRegs()
554 Reserved.set(X86::SSP); in getReservedRegs()
556 // Set the instruction pointer register and its aliases as reserved. in getReservedRegs()
558 Reserved.set(SubReg); in getReservedRegs()
560 // Set the frame-pointer register and its aliases as reserved if needed. in getReservedRegs()
561 if (TFI->hasFP(MF)) { in getReservedRegs()
563 Reserved.set(SubReg); in getReservedRegs()
566 // Set the base-pointer register and its aliases as reserved if needed. in getReservedRegs()
577 Reserved.set(SubReg); in getReservedRegs()
581 Reserved.set(X86::CS); in getReservedRegs()
582 Reserved.set(X86::SS); in getReservedRegs()
583 Reserved.set(X86::DS); in getReservedRegs()
584 Reserved.set(X86::ES); in getReservedRegs()
585 Reserved.set(X86::FS); in getReservedRegs()
586 Reserved.set(X86::GS); in getReservedRegs()
590 Reserved.set(X86::ST0 + n); in getReservedRegs()
592 // Reserve the registers that only exist in 64-bit mode. in getReservedRegs()
594 // These 8-bit registers are part of the x86-64 extension even though their in getReservedRegs()
595 // super-registers are old 32-bits. in getReservedRegs()
596 Reserved.set(X86::SIL); in getReservedRegs()
597 Reserved.set(X86::DIL); in getReservedRegs()
598 Reserved.set(X86::BPL); in getReservedRegs()
599 Reserved.set(X86::SPL); in getReservedRegs()
600 Reserved.set(X86::SIH); in getReservedRegs()
601 Reserved.set(X86::DIH); in getReservedRegs()
602 Reserved.set(X86::BPH); in getReservedRegs()
603 Reserved.set(X86::SPH); in getReservedRegs()
608 Reserved.set(*AI); in getReservedRegs()
612 Reserved.set(*AI); in getReservedRegs()
619 Reserved.set(*AI); in getReservedRegs()
625 Reserved.set(X86::R16, X86::R31WH + 1); in getReservedRegs()
629 Reserved.set(*AI); in getReservedRegs()
631 Reserved.set(*AI); in getReservedRegs()
647 // AVX512 registers (X/YMM16-31, ZMM0-31, K registers) in getNumSupportedRegs()
649 // APX registers (R16-R31) in getNumSupportedRegs()
727 return RC->getID() == X86::TILERegClassID; in isTileRegisterClass()
731 // Check if the EFLAGS register is marked as live-out. This shouldn't happen, in adjustStackMapLiveOutMask()
735 // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding in adjustStackMapLiveOutMask()
739 "EFLAGS are not live-out from a patchpoint."); in adjustStackMapLiveOutMask()
746 //===----------------------------------------------------------------------===//
748 //===----------------------------------------------------------------------===//
758 if (X86FI->getStackPtrSaveMI() != nullptr) in hasBasePointer()
761 if (X86FI->hasPreallocatedCall()) in hasBasePointer()
770 // pointer. When we have dynamic allocas or stack-adjusting inline asm, we in hasBasePointer()
787 if (!MRI->canReserveReg(FramePtr)) in canRealignStack()
793 return MRI->canReserveReg(BasePtr); in canRealignStack()
804 // tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
805 // of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
810 unsigned Opc = II->getOpcode(); in tryOptimizeLEAtoMOV()
819 // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will in tryOptimizeLEAtoMOV()
820 // be replaced with a 32-bit operand MOV which will zero extend the upper in tryOptimizeLEAtoMOV()
821 // 32-bits of the super register. in tryOptimizeLEAtoMOV()
826 MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo(); in tryOptimizeLEAtoMOV()
827 TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr, in tryOptimizeLEAtoMOV()
868 // Offset is a 32-bit integer. in eliminateFrameIndex()
872 "Requesting 64-bit offset in 32-bit immediate!"); in eliminateFrameIndex()
904 TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0).getFixed(); in eliminateFrameIndex()
905 } else if (TFI->Is64Bit && (MBB.isEHFuncletEntry() || IsEHFuncletEpilogue)) { in eliminateFrameIndex()
906 FIOffset = TFI->getWin64EHFrameIndexRef(MF, FrameIndex, BasePtr); in eliminateFrameIndex()
908 FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed(); in eliminateFrameIndex()
912 // simple FP case, and doesn't work with stack realignment. On 32-bit, the in eliminateFrameIndex()
913 // offset is from the traditional base pointer location. On 64-bit, the in eliminateFrameIndex()
923 // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit in eliminateFrameIndex()
925 // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided. in eliminateFrameIndex()
948 // Offset is a 32-bit integer. in eliminateFrameIndex()
952 "Requesting 64-bit offset in 32-bit immediate!"); in eliminateFrameIndex()
967 if (MF->callsEHReturn()) in findDeadCallerSavedReg()
975 switch (MBBI->getOpcode()) { in findDeadCallerSavedReg()
993 for (MachineOperand &MO : MBBI->operands()) { in findDeadCallerSavedReg()
1014 return TFI->hasFP(MF) ? FramePtr : StackPtr; in getFrameRegister()
1037 if (VRM->hasShape(VirtReg)) in getTileShape()
1038 return VRM->getShape(VirtReg); in getTileShape()
1040 const MachineOperand &Def = *MRI->def_begin(VirtReg); in getTileShape()
1042 unsigned OpCode = MI->getOpcode(); in getTileShape()
1048 Register SrcReg = MI->getOperand(1).getReg(); in getTileShape()
1050 VRM->assignVirt2Shape(VirtReg, Shape); in getTileShape()
1065 MachineOperand &MO1 = MI->getOperand(1); in getTileShape()
1066 MachineOperand &MO2 = MI->getOperand(2); in getTileShape()
1068 VRM->assignVirt2Shape(VirtReg, Shape); in getTileShape()
1080 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getRegAllocationHints()
1090 Register VReg = Matrix->getOneVReg(PhysReg); in getRegAllocationHints()
1104 if (RC.contains(Hint) && !MRI->isReserved(Hint)) in getRegAllocationHints()
1109 !MRI->isReserved(PhysReg)) in getRegAllocationHints()
1113 #define DEBUG_TYPE "tile-hint" in getRegAllocationHints()