Lines Matching full:src1
97 (ins VR128:$src1, VR128:$src2),
98 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
100 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
103 (ins VR128:$src1, i128mem:$src2),
104 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
106 (vt128 (OpNode (vt128 VR128:$src1),
110 (ins i128mem:$src1, VR128:$src2),
111 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
113 (vt128 (OpNode (vt128 (load addr:$src1)),
119 (ins VR128:$src1, VR128:$src2),
120 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
143 (ins VR128:$src1, u8imm:$src2),
144 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
146 (vt128 (OpNode (vt128 VR128:$src1), timm:$src2)))]>,
149 (ins i128mem:$src1, u8imm:$src2),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
152 (vt128 (OpNode (vt128 (load addr:$src1)), timm:$src2)))]>,
172 (ins VR128:$src1, VR128:$src2, VR128:$src3),
174 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
176 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP, VVVV,
179 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
181 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
183 (Int VR128:$src1, (load addr:$src2),
217 def : Pat<(v8i16 (add (mul (v8i16 VR128:$src1), (v8i16 VR128:$src2)),
219 (VPMACSWWrr VR128:$src1, VR128:$src2, VR128:$src3)>;
220 def : Pat<(v4i32 (add (mul (v4i32 VR128:$src1), (v4i32 VR128:$src2)),
222 (VPMACSDDrr VR128:$src1, VR128:$src2, VR128:$src3)>;
223 def : Pat<(v2i64 (add (X86pmuldq (bc_v2i64 (X86PShufd (v4i32 VR128:$src1), (i8 -11))),
226 (VPMACSDQHrr VR128:$src1, VR128:$src2, VR128:$src3)>;
227 def : Pat<(v2i64 (add (X86pmuldq (v2i64 VR128:$src1), (v2i64 VR128:$src2)),
229 (VPMACSDQLrr VR128:$src1, VR128:$src2, VR128:$src3)>;
230 def : Pat<(v4i32 (add (X86vpmaddwd (v8i16 VR128:$src1), (v8i16 VR128:$src2)),
232 (VPMADCSWDrr VR128:$src1, VR128:$src2, VR128:$src3)>;
249 (ins VR128:$src1, VR128:$src2, u8imm:$cc),
251 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
253 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
257 (ins VR128:$src1, i128mem:$src2, u8imm:$cc),
259 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
261 (vt128 (OpNode (vt128 VR128:$src1),
268 (vt128 VR128:$src1), timm:$cc),
269 (!cast<Instruction>(NAME#"mi") VR128:$src1, addr:$src2,
285 (ins VR128:$src1, VR128:$src2, VR128:$src3),
287 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
289 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
293 (ins VR128:$src1, VR128:$src2, i128mem:$src3),
295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
297 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
301 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
303 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
305 (v16i8 (OpNode (vt128 VR128:$src1), (vt128 (load addr:$src2)),
316 (ins VR128:$src1, VR128:$src2, VR128:$src3),
318 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
332 (ins RC:$src1, RC:$src2, RC:$src3),
334 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
335 [(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
341 (ins RC:$src1, RC:$src2, x86memop:$src3),
343 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
347 (ins RC:$src1, x86memop:$src2, RC:$src3),
349 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
350 [(set RC:$dst, (VT (or (and RC:$src3, RC:$src1),
361 (ins RC:$src1, RC:$src2, RC:$src3),
363 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
375 def : Pat<(v16i8 (or (and VR128:$src3, VR128:$src1),
377 (VPCMOVrrr VR128:$src1, VR128:$src2, VR128:$src3)>;
378 def : Pat<(v8i16 (or (and VR128:$src3, VR128:$src1),
380 (VPCMOVrrr VR128:$src1, VR128:$src2, VR128:$src3)>;
381 def : Pat<(v4i32 (or (and VR128:$src3, VR128:$src1),
383 (VPCMOVrrr VR128:$src1, VR128:$src2, VR128:$src3)>;
385 def : Pat<(or (and VR128:$src3, VR128:$src1),
387 (VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>;
388 def : Pat<(or (and VR128:$src3, VR128:$src1),
390 (VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>;
391 def : Pat<(or (and VR128:$src3, VR128:$src1),
393 (VPCMOVrmr VR128:$src1, addr:$src2, VR128:$src3)>;
395 def : Pat<(v32i8 (or (and VR256:$src3, VR256:$src1),
397 (VPCMOVYrrr VR256:$src1, VR256:$src2, VR256:$src3)>;
398 def : Pat<(v16i16 (or (and VR256:$src3, VR256:$src1),
400 (VPCMOVYrrr VR256:$src1, VR256:$src2, VR256:$src3)>;
401 def : Pat<(v8i32 (or (and VR256:$src3, VR256:$src1),
403 (VPCMOVYrrr VR256:$src1, VR256:$src2, VR256:$src3)>;
405 def : Pat<(or (and VR256:$src3, VR256:$src1),
407 (VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>;
408 def : Pat<(or (and VR256:$src3, VR256:$src1),
410 (VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>;
411 def : Pat<(or (and VR256:$src3, VR256:$src1),
413 (VPCMOVYrmr VR256:$src1, addr:$src2, VR256:$src3)>;
421 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4),
423 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
425 (VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 timm:$src4))))]>,
428 (ins RC:$src1, RC:$src2, intmemop:$src3, u4imm:$src4),
430 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
432 (VT (X86vpermil2 RC:$src1, RC:$src2, (IntLdFrag addr:$src3),
436 (ins RC:$src1, fpmemop:$src2, RC:$src3, u4imm:$src4),
438 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
440 (VT (X86vpermil2 RC:$src1, (FPLdFrag addr:$src2),
450 (ins RC:$src1, RC:$src2, RC:$src3, u4imm:$src4),
452 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),