Lines Matching +full:sdi +full:- +full:enabled
1 //===-- X86InstrUtils.td - X86 Instruction Utilities --------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
17 // Prefix byte classes which are used to indicate to the ad-hoc machine code
59 // Specify AVX512 8-bit compressed displacement encoding based on the vector
110 // NDD - Helper for new data destination instructions
118 // NF - Helper for NF (no flags update) instructions
120 // PL - Helper for promoted legacy instructions
122 // ZU - Helper for Zero Upper instructions
125 //===----------------------------------------------------------------------===//
127 //===----------------------------------------------------------------------===//
129 /// X86TypeInfo - This is a bunch of information that describes relevant X86
138 /// VT - This is the value type itself.
141 /// InstrSuffix - This is the suffix used on instructions with this type. For
142 /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q".
145 /// RegClass - This is the register class associated with this type. For
146 /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64.
149 /// LoadNode - This is the load node associated with this type. For
150 /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64.
153 /// MemOperand - This is the memory operand associated with this type. For
154 /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem.
157 /// ImmEncoding - This is the encoding of an immediate of this type. For
158 /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32
159 /// since the immediate fields of i64 instructions is a 32-bit sign extended
163 /// ImmOperand - This is the operand kind of an immediate of this type. For
164 /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 ->
165 /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign
169 /// ImmOperator - This is the operator that should be used to match an
175 /// Imm8Operand - This is the operand kind to use for an imm8 of this type.
176 /// For example, i8 -> <invalid>, i16 -> i16i8imm, i32 -> i32i8imm. This is
177 /// only used for instructions that have a sign-extended imm8 field form.
180 /// Imm8Operator - This is the operator that should be used to match an 8-bit
186 /// HasEvenOpcode - This bit is true if the instruction should have an even (as
191 /// HasREX_W - This bit is set to true if the instruction should have
229 // Corresponding write-mask register class.
255 // "i" for integer types and "f" for floating-point types
264 // FP scalar memory operand for intrinsics - ssmem/sdmem.
286 // 8-bit compressed displacement tuple/subvector format. This is only
339 // We map scalar types to the smallest (128-bit) vector type
448 // FPI - Floating Point Instruction template.
455 // FpI_ - Floating Point Pseudo Instruction template.
463 // Templates for instructions that use a 16- or 32-bit segmented address as
466 // Iseg16 - 16-bit segment selector, 16-bit offset
467 // Iseg32 - 16-bit segment selector, 32-bit offset
481 // SI - SSE 1 & 2 scalar instructions
498 // SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512
514 // SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512
529 // PI - SSE 1 & 2 packed instructions
544 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
552 // PIi8 - SSE 1 & 2 packed instructions with immediate
569 // SSI - SSE1 instructions with XS prefix.
570 // PSI - SSE1 instructions with PS prefix.
571 // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix.
572 // VSSI - SSE1 instructions with XS prefix in AVX form.
573 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single.
600 // SDI - SSE2 instructions with XD prefix.
601 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
602 // S2SI - SSE2 instructions with XS prefix.
603 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
604 // PDI - SSE2 instructions with PD prefix, packed double domain.
605 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
606 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
607 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
609 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
610 // S2I - SSE2 scalar instructions with PD prefix.
611 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
613 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
616 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
664 // S3I - SSE3 instructions with PD prefixes.
665 // S3SI - SSE3 instructions with XS prefix.
666 // S3DI - SSE3 instructions with XD prefix.
684 // SS38I - SSSE3 instructions with T8 prefix.
685 // SS3AI - SSSE3 instructions with TA prefix.
686 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
687 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
689 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
690 // uses the MMX registers. The 64-bit versions are grouped with the MMX
691 // classes. They need to be enabled even if AVX is enabled.
712 // SS48I - SSE 4.1 instructions with T8 prefix.
713 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
726 // SS428I - SSE 4.2 instructions with T8 prefix.
741 // AVX8I - AVX instructions with T8, PD prefix.
742 // AVXAIi8 - AVX instructions with TA, PD prefix and ImmT = Imm8.
755 // AVX28I - AVX2 instructions with T8, PD prefix.
756 // AVX2AIi8 - AVX2 instructions with TA, PD prefix and ImmT = Imm8.
767 // AVX-512 Instruction Templates:
768 // Instructions introduced in AVX-512 (no SSE equivalent forms)
770 // AVX5128I - AVX-512 instructions with T8, PD prefix.
771 // AVX512AIi8 - AVX-512 instructions with TA, PD prefix and ImmT = Imm8.
772 // AVX512PDI - AVX-512 instructions with PD, double packed.
773 // AVX512PSI - AVX-512 instructions with PS, single packed.
774 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
775 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
776 // AVX512BI - AVX-512 instructions with PD, int packed domain.
777 // AVX512SI - AVX-512 scalar instructions with PD prefix.
913 // X86-64 Instruction templates...
944 // MMXI - MMX instructions with TB prefix.
945 // MMXRI - MMX instructions with TB prefix and REX.W.
946 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
958 /// ITy - This instruction base class takes the type info for the instruction.
975 // BinOpRR - Instructions that read "reg, reg".
979 // BinOpRR_F - Instructions that read "reg, reg" and write EFLAGS only.
984 // BinOpRR_F_Rev - Reversed encoding of BinOpRR_F
989 // BinOpRR_R - Instructions that read "reg, reg" and write "reg".
993 // BinOpRR_R_Rev - Reversed encoding of BinOpRR_R
998 // BinOpRR_RF - Instructions that read "reg, reg", and write "reg", EFLAGS.
1004 // BinOpRR_RF_Rev - Reversed encoding of BinOpRR_RF.
1009 // BinOpRRF_RF - Instructions that read "reg, reg", write "reg" and read/write
1018 // BinOpRRF_RF_Rev - Reversed encoding of BinOpRRF_RF
1024 // BinOpRM - Instructions that read "reg, [mem]".
1031 // BinOpRM_F - Instructions that read "reg, [mem]" and write EFLAGS only.
1036 // BinOpRM_R - Instructions that read "reg, [mem]", and write "reg".
1040 // BinOpRM_RF - Instructions that read "reg, [mem]", and write "reg", EFLAGS.
1045 // BinOpRMF_RF - Instructions that read "reg, [mem]", write "reg" and read/write
1059 // BinOpRI - Instructions that read "reg, imm".
1065 // BinOpRI_F - Instructions that read "reg, imm" and write EFLAGS only.
1071 // BinOpRI_R - Instructions that read "reg, imm" and write "reg".
1075 // BinOpRI8U_R - Instructions that read "reg, u8imm" and write "reg".
1082 // BinOpRI_RF - Instructions that read "reg, imm" and write "reg", EFLAGS.
1087 // BinOpRIF_RF - Instructions that read "reg, imm", write "reg" and read/write
1096 // BinOpRI8 - Instructions that read "reg, imm8".
1102 // BinOpRI8_F - Instructions that read "reg, imm8" and write EFLAGS only.
1105 // BinOpRI8_R - Instructions that read "reg, imm8" and write "reg".
1108 // BinOpRI8_RF - Instructions that read "reg, imm8" and write "reg", EFLAGS.
1111 // BinOpRI8F_RF - Instructions that read "reg, imm", write "reg" and read/write
1118 // BinOpMR - Instructions that read "[mem], reg".
1125 // BinOpMR_R - Instructions that read "[mem], reg", and write "reg".
1128 // BinOpMR_RF - Instructions that read "[mem], reg", and write "reg", EFLAGS.
1133 // BinOpMR_F - Instructions that read "[mem], imm8" and write EFLAGS only.
1139 // BinOpMR_M - Instructions that read "[mem], reg" and write "[mem]".
1147 // BinOpMR_MF - Instructions that read "[mem], reg" and write "[mem]", EFLAGS.
1159 // BinOpMRF_RF - Instructions that read "[mem], reg", write "reg" and
1166 // BinOpMRF_MF - Instructions that read "[mem], reg", write "[mem]" and
1182 // BinOpMI - Instructions that read "[mem], imm".
1189 // BinOpMI_F - Instructions that read "[mem], imm" and write EFLAGS only.
1195 // BinOpMI_R - Instructions that read "[mem], imm" and write "reg".
1199 // BinOpMI_R - Instructions that read "[mem], imm" and write "reg", EFLAGS.
1205 // BinOpMI_M - Instructions that read "[mem], imm" and write "[mem]".
1210 // BinOpMI_MF - Instructions that read "[mem], imm" and write "[mem]", EFLAGS.
1218 // BinOpMIF_RF - Instructions that read "[mem], imm", write "reg" and
1225 // BinOpMIF_MF - Instructions that read "[mem], imm", write "[mem]" and
1235 // BinOpMI8 - Instructions that read "[mem], imm8".
1242 // BinOpMI8U - Instructions that read "[mem], u8imm".
1248 // BinOpMI8_F - Instructions that read "[mem], imm8" and write EFLAGS only.
1251 // BinOpMI8_R - Instructions that read "[mem], imm8" and write "reg".
1254 // BinOpMI8U_R - Instructions that read "[mem], u8imm" and write "reg".
1258 // BinOpMI8_RF - Instructions that read "[mem], imm8" and write "reg"/EFLAGS.
1261 // BinOpMI8_M - Instructions that read "[mem], imm8" and write "[mem]".
1266 // BinOpMI8U_M - Instructions that read "[mem], u8imm" and write "[mem]".
1272 // BinOpMI8_MF - Instructions that read "[mem], imm8" and write "[mem]", EFLAGS.
1277 // BinOpMI8F_RF - Instructions that read "[mem], imm8", write "reg" and
1282 // BinOpMI8F_MF - Instructions that read "[mem], imm8", write "[mem]" and
1289 // BinOpAI - Instructions that read "a-reg imm" (Accumulator register).
1296 // BinOpAI_F - Instructions that read "a-reg imm" and write EFLAGS only.
1300 // BinOpAI_AF - Instructions that read "a-reg imm" and write a-reg/EFLAGS.
1305 // BinOpAIF_AF - Instructions that read "a-reg imm", write a-reg and read/write
1313 // BinOpRC_R - Instructions that read "reg, cl" and write reg.
1320 // BinOpMC_M - Instructions that read "[mem], cl" and write [mem].
1328 // BinOpMC_R - Instructions that read "[mem], cl" and write reg.
1336 // UnaryOpR - Instructions that read "reg".
1340 // UnaryOpR_R - Instructions that read "reg" and write "reg".
1346 // UnaryOpR_RF - Instructions that read "reg" and write "reg"/EFLAGS.
1354 // UnaryOpM - Instructions that read "[mem]".
1360 // UnaryOpM_R - Instructions that read "[mem]" and writes "reg".
1366 // UnaryOpM_RF - Instructions that read "[mem]" and writes "reg"/EFLAGS.
1372 // UnaryOpM_M - Instructions that read "[mem]" and writes "[mem]".
1380 // UnaryOpM_MF - Instructions that read "[mem]" and writes "[mem]"/EFLAGS.