Lines Matching full:src2
304 def : Pat<(rotl GR8:$src1, (i8 relocImm:$src2)),
305 (ROL8ri GR8:$src1, relocImm:$src2)>;
306 def : Pat<(rotl GR16:$src1, (i8 relocImm:$src2)),
307 (ROL16ri GR16:$src1, relocImm:$src2)>;
308 def : Pat<(rotl GR32:$src1, (i8 relocImm:$src2)),
309 (ROL32ri GR32:$src1, relocImm:$src2)>;
310 def : Pat<(rotl GR64:$src1, (i8 relocImm:$src2)),
311 (ROL64ri GR64:$src1, relocImm:$src2)>;
313 def : Pat<(rotr GR8:$src1, (i8 relocImm:$src2)),
314 (ROR8ri GR8:$src1, relocImm:$src2)>;
315 def : Pat<(rotr GR16:$src1, (i8 relocImm:$src2)),
316 (ROR16ri GR16:$src1, relocImm:$src2)>;
317 def : Pat<(rotr GR32:$src1, (i8 relocImm:$src2)),
318 (ROR32ri GR32:$src1, relocImm:$src2)>;
319 def : Pat<(rotr GR64:$src1, (i8 relocImm:$src2)),
320 (ROR64ri GR64:$src1, relocImm:$src2)>;
323 def : Pat<(rotl GR8:$src1, (i8 relocImm:$src2)),
324 (ROL8ri_ND GR8:$src1, relocImm:$src2)>;
325 def : Pat<(rotl GR16:$src1, (i8 relocImm:$src2)),
326 (ROL16ri_ND GR16:$src1, relocImm:$src2)>;
327 def : Pat<(rotl GR32:$src1, (i8 relocImm:$src2)),
328 (ROL32ri_ND GR32:$src1, relocImm:$src2)>;
329 def : Pat<(rotl GR64:$src1, (i8 relocImm:$src2)),
330 (ROL64ri_ND GR64:$src1, relocImm:$src2)>;
332 def : Pat<(rotr GR8:$src1, (i8 relocImm:$src2)),
333 (ROR8ri_ND GR8:$src1, relocImm:$src2)>;
334 def : Pat<(rotr GR16:$src1, (i8 relocImm:$src2)),
335 (ROR16ri_ND GR16:$src1, relocImm:$src2)>;
336 def : Pat<(rotr GR32:$src1, (i8 relocImm:$src2)),
337 (ROR32ri_ND GR32:$src1, relocImm:$src2)>;
338 def : Pat<(rotr GR64:$src1, (i8 relocImm:$src2)),
339 (ROR64ri_ND GR64:$src1, relocImm:$src2)>;
348 (ins t.RegClass:$src1, t.RegClass:$src2, u8imm:$src3), m, !if(!eq(ndd, 0), triop_args, triop_ndd_args),
354 [(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2, (i8 imm:$src3)))],
355 [(set t.RegClass:$dst, (node t.RegClass:$src2, t.RegClass:$src1, (i8 imm:$src3)))]);
363 [(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2, CL))],
364 [(set t.RegClass:$dst, (node t.RegClass:$src2, t.RegClass:$src1, CL))]);
368 : ITy<o, MRMDestMem, t, (outs), (ins t.MemOperand:$src1, t.RegClass:$src2, u8imm:$src3),
375 [(store (node (t.LoadNode addr:$src1), t.RegClass:$src2, (i8 imm:$src3)), addr:$src1)],
376 [(store (node t.RegClass:$src2, (t.LoadNode addr:$src1), (i8 imm:$src3)), addr:$src1)]);
385 [(store (node (t.LoadNode addr:$src1), t.RegClass:$src2, CL), addr:$src1)],
386 [(store (node t.RegClass:$src2, (t.LoadNode addr:$src1), CL), addr:$src1)]);
390 : ITy<o, MRMDestMem, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, t.RegClass:$src2, u8imm:$src3),
396 [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1), t.RegClass:$src2, (i8 imm:$src3)))],
397 [(set t.RegClass:$dst, (node t.RegClass:$src2, (t.LoadNode addr:$src1), (i8 imm:$src3)))]);
405 [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1), t.RegClass:$src2, CL))],
406 [(set t.RegClass:$dst, (node t.RegClass:$src2, (t.LoadNode addr:$src1), CL))]);
542 : ITy<0xF0, MRMSrcReg, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, u8imm:$src2),
547 : ITy<0xF0, MRMSrcMem, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, u8imm:$src2),
568 : ITy<0xF7, MRMSrcReg4VOp3, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, t.RegClass:$src2),
572 : ITy<0xF7, MRMSrcMem4VOp3, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, t.RegClass:$src2),
578 // RC:$src2
642 def : Pat<(op GR32:$src1, GR8:$src2),
644 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
645 def : Pat<(op GR64:$src1, GR8:$src2),
647 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
648 def : Pat<(op GR32:$src1, (shiftMask32 GR8:$src2)),
650 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
651 def : Pat<(op GR64:$src1, (shiftMask64 GR8:$src2)),
653 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
665 def : Pat<(op (loadi32 addr:$src1), GR8:$src2),
667 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
668 def : Pat<(op (loadi64 addr:$src1), GR8:$src2),
670 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
671 def : Pat<(op (loadi32 addr:$src1), (shiftMask32 GR8:$src2)),
673 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
674 def : Pat<(op (loadi64 addr:$src1), (shiftMask64 GR8:$src2)),
676 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;