Lines Matching +full:0 +full:xd1
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
22 let isConvertibleToThreeAddress = !if(!eq(m, "shl"), 1, 0) in {
61 def 8r1 : UnaryOpR_RF<0xD1, RegMRM, m, Xi8>;
62 def 16r1 : UnaryOpR_RF<0xD1, RegMRM, m, Xi16>, OpSize16;
63 def 32r1 : UnaryOpR_RF<0xD1, RegMRM, m, Xi32>, OpSize32;
64 def 64r1 : UnaryOpR_RF<0xD1, RegMRM, m, Xi64>;
73 def 8r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi8, null_frag, 1>, DisassembleOnly;
74 def 16r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi16, null_frag, 1>, PD;
75 def 32r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi32, null_frag, 1>;
76 def 64r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi64, null_frag, 1>;
78 def 8r1_EVEX : UnaryOpR_RF<0xD1, RegMRM, m, Xi8>, PL;
79 def 16r1_EVEX : UnaryOpR_RF<0xD1, RegMRM, m, Xi16>, PL, PD;
80 def 32r1_EVEX : UnaryOpR_RF<0xD1, RegMRM, m, Xi32>, PL;
81 def 64r1_EVEX : UnaryOpR_RF<0xD1, RegMRM, m, Xi64>, PL;
86 def 8m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi8>;
87 def 16m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi16>, OpSize16;
88 def 32m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi32>, OpSize32;
89 def 64m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi64>, Requires<[In64BitMode]>;
92 def 8m1_EVEX : UnaryOpM_MF<0xD1, MemMRM, m, Xi8>, PL;
93 def 16m1_EVEX : UnaryOpM_MF<0xD1, MemMRM, m, Xi16>, PL, PD;
94 def 32m1_EVEX : UnaryOpM_MF<0xD1, MemMRM, m, Xi32>, PL;
95 def 64m1_EVEX : UnaryOpM_MF<0xD1, MemMRM, m, Xi64>, PL;
99 def 8m1_ND : UnaryOpM_RF<0xD1, MemMRM, m, Xi8>;
100 def 16m1_ND : UnaryOpM_RF<0xD1, MemMRM, m, Xi16>, PD;
101 def 32m1_ND : UnaryOpM_RF<0xD1, MemMRM, m, Xi32>;
102 def 64m1_ND : UnaryOpM_RF<0xD1, MemMRM, m, Xi64>;
150 let isConvertibleToThreeAddress = !if(!eq(m, "shl"), 1, 0) in {
179 def 8r1_NF : UnaryOpR_R<0xD1, RegMRM, m, Xi8>, NF;
180 def 16r1_NF : UnaryOpR_R<0xD1, RegMRM, m, Xi16>, NF, PD;
181 def 32r1_NF : UnaryOpR_R<0xD1, RegMRM, m, Xi32>, NF;
182 def 64r1_NF : UnaryOpR_R<0xD1, RegMRM, m, Xi64>, NF;
184 def 8r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi8, null_frag, 1>, EVEX_NF, DisassembleOnly;
185 def 16r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi16, null_frag, 1>, EVEX_NF, PD;
186 def 32r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi32, null_frag, 1>, EVEX_NF;
187 def 64r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi64, null_frag, 1>, EVEX_NF;
191 def 8m1_NF : UnaryOpM_M<0xD1, MemMRM, m, Xi8>, NF;
192 def 16m1_NF : UnaryOpM_M<0xD1, MemMRM, m, Xi16>, NF, PD;
193 def 32m1_NF : UnaryOpM_M<0xD1, MemMRM, m, Xi32>, NF;
194 def 64m1_NF : UnaryOpM_M<0xD1, MemMRM, m, Xi64>, NF;
197 def 8m1_NF_ND : UnaryOpM_R<0xD1, MemMRM, m, Xi8>, EVEX_NF;
198 def 16m1_NF_ND : UnaryOpM_R<0xD1, MemMRM, m, Xi16>, EVEX_NF, PD;
199 def 32m1_NF_ND : UnaryOpM_R<0xD1, MemMRM, m, Xi32>, EVEX_NF;
200 def 64m1_NF_ND : UnaryOpM_R<0xD1, MemMRM, m, Xi64>, EVEX_NF;
346 class ShlrdOpRRI8U_R<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node = null_frag, bit ndd = 0>
348 (ins t.RegClass:$src1, t.RegClass:$src2, u8imm:$src3), m, !if(!eq(ndd, 0), triop_args, triop_ndd_args),
358 class ShlrdOpRRC_R<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node = null_frag, bit ndd = 0>
359 : BinOpRR<o, m, !if(!eq(ndd, 0), triop_cl_args, triop_cl_ndd_args), t, (outs t.RegClass:$dst), []>, NDD<ndd> {
500 defm SHLD : Shlrd<0xA4, 0xA5, 0x24, "shld", fshl, X86fshl>;
501 defm SHRD : Shlrd<0xAC, 0xAD, 0x2C, "shrd", fshr, X86fshr>;
510 def SHLDROT32ri : I<0, Pseudo, (outs GR32:$dst),
513 def SHLDROT64ri : I<0, Pseudo, (outs GR64:$dst),
517 def SHRDROT32ri : I<0, Pseudo, (outs GR32:$dst),
520 def SHRDROT64ri : I<0, Pseudo, (outs GR64:$dst),
542 : ITy<0xF0, MRMSrcReg, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, u8imm:$src2),
547 : ITy<0xF0, MRMSrcMem, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, u8imm:$src2),
568 : ITy<0xF7, MRMSrcReg4VOp3, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, t.RegClass:$src2),
572 : ITy<0xF7, MRMSrcMem4VOp3, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, t.RegClass:$src2),