Lines Matching refs:XD
273 SSEPackedDouble, UseSSE2>, TB, XD;
279 SSEPackedDouble>, TB, XD;
914 TB, XD, VEX, VEX_LIG;
918 TB, XD, VEX, REX_W, VEX_LIG;
931 TB, XD, VEX, VEX_LIG;
935 TB, XD, VEX, REX_W, VEX_LIG;
950 WriteCvtI2SD, SSEPackedDouble>, TB, XD, VEX, VVVV,
953 WriteCvtI2SD, SSEPackedDouble>, TB, XD, VEX, VVVV,
992 WriteCvtSD2I, SSEPackedDouble>, TB, XD, SIMD_EXC;
995 WriteCvtSD2I, SSEPackedDouble>, TB, XD, REX_W, SIMD_EXC;
1005 WriteCvtSD2I, SSEPackedDouble>, TB, XD, SIMD_EXC;
1008 WriteCvtSD2I, SSEPackedDouble>, TB, XD, REX_W, SIMD_EXC;
1018 WriteCvtI2SD, SSEPackedDouble, ReadInt2Fpu>, TB, XD;
1021 WriteCvtI2SD, SSEPackedDouble, ReadInt2Fpu>, TB, XD, REX_W, SIMD_EXC;
1077 WriteCvtSD2I, SSEPackedDouble>, TB, XD, VEX, VEX_LIG;
1080 WriteCvtSD2I, SSEPackedDouble>, TB, XD, VEX, REX_W, VEX_LIG;
1084 SSEPackedDouble>, TB, XD;
1087 SSEPackedDouble>, TB, XD, REX_W;
1099 TB, XD, VEX, VVVV, VEX_LIG;
1102 TB, XD, VEX, VVVV, VEX_LIG, REX_W, SIMD_EXC;
1113 TB, XD;
1116 TB, XD, REX_W, SIMD_EXC;
1160 WriteCvtSS2I, SSEPackedDouble>, TB, XD, VEX, VEX_LIG;
1164 TB, XD, VEX, VEX_LIG, REX_W;
1176 WriteCvtSD2I, SSEPackedDouble>, TB, XD;
1180 TB, XD, REX_W;
1298 TB, XD, VEX, VVVV, VEX_LIG, WIG,
1314 TB, XD, Requires<[UseSSE2, OptForSize]>,
1324 TB, XD, VEX, VVVV, VEX_LIG, WIG, Requires<[UseAVX]>,
1331 TB, XD, VEX, VVVV, VEX_LIG, WIG, Requires<[UseAVX]>,
1339 TB, XD, Requires<[UseSSE2]>, Sched<[WriteCvtSD2SS]>;
1345 TB, XD, Requires<[UseSSE2]>,
1881 TB, XD, VEX, VVVV, VEX_LIG, WIG;
1891 SchedWriteFCmpSizes.PD.Scl, sse_load_f64>, TB, XD;
2684 TB, XD, VEX, VVVV, VEX_LIG, WIG;
2692 sched.PD.Scl>, TB, XD;
2706 SSEPackedDouble, sched.PD.Scl, 0>, TB, XD, VEX, VVVV, VEX_LIG, WIG;
2714 SSEPackedDouble, sched.PD.Scl>, TB, XD;
3051 sdmem, OpNode, SSEPackedDouble, sched.Scl, UseSSE2>, TB, XD;
3054 TB, XD, VEX, VVVV, VEX_LIG, WIG;
3777 SchedWriteShuffle, NoVLX_Or_NoBWI>, TB, XD;
4579 TB, XD, VEX, VVVV, WIG;
4582 TB, XD, VEX, VVVV, VEX_L, WIG;
4596 SchedWriteFAddSizes.PS.XMM, memopv4f32>, TB, XD;
6708 let Predicates = [HasCRC32, NoEGPR], OpMap = T8, OpPrefix = XD in {
7043 TB, XD, Sched<[SchedWriteVecALU.XMM]>;
7049 TB, XD, Sched<[SchedWriteVecALU.XMM]>;
7060 "movntsd\t{$src, $dst|$dst, $src}", []>, TB, XD;
8241 1>, T8, XD;
8244 1>, VEX_L, T8, XD;
8253 1>, T8, XD;
8256 1>, VEX_L, T8, XD;
8321 f256mem>, T8, XD;
8348 VEX, T8, XD, Sched<[WriteVecIMul]>;
8354 VEX, T8, XD, Sched<[WriteVecIMul]>;
8360 VEX_L, VEX, VVVV, T8, XD, Sched<[WriteVecIMul]>;
8425 defm VSM4RNDS4 : SM4_Base<"vsm4rnds4", VR128, "128", loadv4i32, i128mem>, T8, XD, VEX, VVVV;
8426 defm VSM4RNDS4Y : SM4_Base<"vsm4rnds4", VR256, "256", loadv8i32, i256mem>, T8, XD, VEX_L, VEX, VVVV;