Lines Matching refs:TB
271 SSEPackedSingle, UseSSE1>, TB, XS;
273 SSEPackedDouble, UseSSE2>, TB, XD;
277 SSEPackedSingle>, TB, XS;
279 SSEPackedDouble>, TB, XD;
355 TB, VEX, WIG;
358 TB, PD, VEX, WIG;
361 TB, VEX, WIG;
364 TB, PD, VEX, WIG;
368 TB, VEX, VEX_L, WIG;
371 TB, PD, VEX, VEX_L, WIG;
374 TB, VEX, VEX_L, WIG;
377 TB, PD, VEX, VEX_L, WIG;
383 TB;
386 TB;
391 TB, PD;
394 TB, PD;
669 [], SSEPackedSingle>, TB,
677 SSEPackedDouble>, TB, PD,
906 TB, XS, VEX, VEX_LIG;
910 TB, XS, VEX, REX_W, VEX_LIG;
914 TB, XD, VEX, VEX_LIG;
918 TB, XD, VEX, REX_W, VEX_LIG;
923 TB, XS, VEX, VEX_LIG;
927 TB, XS, VEX, REX_W, VEX_LIG;
931 TB, XD, VEX, VEX_LIG;
935 TB, XD, VEX, REX_W, VEX_LIG;
944 WriteCvtI2SS, SSEPackedSingle>, TB, XS, VEX, VVVV,
947 WriteCvtI2SS, SSEPackedSingle>, TB, XS, VEX, VVVV,
950 WriteCvtI2SD, SSEPackedDouble>, TB, XD, VEX, VVVV,
953 WriteCvtI2SD, SSEPackedDouble>, TB, XD, VEX, VVVV,
986 WriteCvtSS2I, SSEPackedSingle>, TB, XS, SIMD_EXC;
989 WriteCvtSS2I, SSEPackedSingle>, TB, XS, REX_W, SIMD_EXC;
992 WriteCvtSD2I, SSEPackedDouble>, TB, XD, SIMD_EXC;
995 WriteCvtSD2I, SSEPackedDouble>, TB, XD, REX_W, SIMD_EXC;
999 WriteCvtSS2I, SSEPackedSingle>, TB, XS, SIMD_EXC;
1002 WriteCvtSS2I, SSEPackedSingle>, TB, XS, REX_W, SIMD_EXC;
1005 WriteCvtSD2I, SSEPackedDouble>, TB, XD, SIMD_EXC;
1008 WriteCvtSD2I, SSEPackedDouble>, TB, XD, REX_W, SIMD_EXC;
1012 WriteCvtI2SS, SSEPackedSingle, ReadInt2Fpu>, TB, XS, SIMD_EXC;
1015 WriteCvtI2SS, SSEPackedSingle, ReadInt2Fpu>, TB, XS, REX_W, SIMD_EXC;
1018 WriteCvtI2SD, SSEPackedDouble, ReadInt2Fpu>, TB, XD;
1021 WriteCvtI2SD, SSEPackedDouble, ReadInt2Fpu>, TB, XD, REX_W, SIMD_EXC;
1077 WriteCvtSD2I, SSEPackedDouble>, TB, XD, VEX, VEX_LIG;
1080 WriteCvtSD2I, SSEPackedDouble>, TB, XD, VEX, REX_W, VEX_LIG;
1084 SSEPackedDouble>, TB, XD;
1087 SSEPackedDouble>, TB, XD, REX_W;
1093 TB, XS, VEX, VVVV, VEX_LIG, SIMD_EXC;
1096 TB, XS, VEX, VVVV, VEX_LIG, REX_W, SIMD_EXC;
1099 TB, XD, VEX, VVVV, VEX_LIG;
1102 TB, XD, VEX, VVVV, VEX_LIG, REX_W, SIMD_EXC;
1107 TB, XS, SIMD_EXC;
1110 TB, XS, REX_W, SIMD_EXC;
1113 TB, XD;
1116 TB, XD, REX_W, SIMD_EXC;
1153 WriteCvtSS2I, SSEPackedSingle>, TB, XS, VEX, VEX_LIG;
1157 TB, XS, VEX, VEX_LIG, REX_W;
1160 WriteCvtSS2I, SSEPackedDouble>, TB, XD, VEX, VEX_LIG;
1164 TB, XD, VEX, VEX_LIG, REX_W;
1169 WriteCvtSS2I, SSEPackedSingle>, TB, XS;
1173 TB, XS, REX_W;
1176 WriteCvtSD2I, SSEPackedDouble>, TB, XD;
1180 TB, XD, REX_W;
1220 WriteCvtSS2I, SSEPackedSingle>, TB, XS, VEX, VEX_LIG;
1223 WriteCvtSS2I, SSEPackedSingle>, TB, XS, VEX, REX_W, VEX_LIG;
1228 WriteCvtSS2I, SSEPackedSingle>, TB, XS;
1231 WriteCvtSS2I, SSEPackedSingle>, TB, XS, REX_W;
1236 TB, VEX, Requires<[HasAVX, NoVLX]>, WIG;
1240 TB, VEX, VEX_L, Requires<[HasAVX, NoVLX]>, WIG;
1245 TB, Requires<[UseSSE2]>;
1298 TB, XD, VEX, VVVV, VEX_LIG, WIG,
1314 TB, XD, Requires<[UseSSE2, OptForSize]>,
1324 TB, XD, VEX, VVVV, VEX_LIG, WIG, Requires<[UseAVX]>,
1331 TB, XD, VEX, VVVV, VEX_LIG, WIG, Requires<[UseAVX]>,
1339 TB, XD, Requires<[UseSSE2]>, Sched<[WriteCvtSD2SS]>;
1345 TB, XD, Requires<[UseSSE2]>,
1356 TB, XS, VEX, VVVV, VEX_LIG, WIG,
1362 TB, XS, VEX, VVVV, VEX_LIG, WIG,
1376 TB, XS, Requires<[UseSSE2]>, Sched<[WriteCvtSS2SD]>, SIMD_EXC;
1380 TB, XS, Requires<[UseSSE2, OptForSize]>,
1389 []>, TB, XS, VEX, VVVV, VEX_LIG, WIG,
1395 []>, TB, XS, VEX, VVVV, VEX_LIG, WIG, Requires<[HasAVX]>,
1401 []>, TB, XS, Requires<[UseSSE2]>,
1407 []>, TB, XS, Requires<[UseSSE2]>,
1715 TB, VEX, Sched<[WriteCvtPS2PD]>, WIG;
1719 TB, VEX, Sched<[WriteCvtPS2PD.Folded]>, WIG;
1723 TB, VEX, VEX_L, Sched<[WriteCvtPS2PDY]>, WIG;
1727 TB, VEX, VEX_L, Sched<[WriteCvtPS2PDY.Folded]>, WIG;
1734 TB, Sched<[WriteCvtPS2PD]>;
1738 TB, Sched<[WriteCvtPS2PD.Folded]>;
1876 TB, XS, VEX, VVVV, VEX_LIG, WIG;
1881 TB, XD, VEX, VVVV, VEX_LIG, WIG;
1887 SchedWriteFCmpSizes.PS.Scl, sse_load_f32>, TB, XS;
1891 SchedWriteFCmpSizes.PD.Scl, sse_load_f64>, TB, XD;
1935 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG, WIG;
1937 "ucomisd", SSEPackedDouble>, TB, PD, VEX, VEX_LIG, WIG;
1939 "comiss", SSEPackedSingle>, TB, VEX, VEX_LIG, WIG;
1941 "comisd", SSEPackedDouble>, TB, PD, VEX, VEX_LIG, WIG;
1945 sse_load_f32, "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG, WIG;
1947 sse_load_f64, "ucomisd", SSEPackedDouble>, TB, PD, VEX, VEX_LIG, WIG;
1950 sse_load_f32, "comiss", SSEPackedSingle>, TB, VEX, VEX_LIG, WIG;
1952 sse_load_f64, "comisd", SSEPackedDouble>, TB, PD, VEX, VEX_LIG, WIG;
1955 "ucomiss", SSEPackedSingle>, TB;
1957 "ucomisd", SSEPackedDouble>, TB, PD;
1959 "comiss", SSEPackedSingle>, TB;
1961 "comisd", SSEPackedDouble>, TB, PD;
1965 sse_load_f32, "ucomiss", SSEPackedSingle>, TB;
1967 sse_load_f64, "ucomisd", SSEPackedDouble>, TB, PD;
1970 sse_load_f32, "comiss", SSEPackedSingle>, TB;
1972 sse_load_f64, "comisd", SSEPackedDouble>, TB, PD;
1995 SchedWriteFCmpSizes.PS.XMM, SSEPackedSingle, loadv4f32>, TB, VEX, VVVV, WIG;
1998 SchedWriteFCmpSizes.PD.XMM, SSEPackedDouble, loadv2f64>, TB, PD, VEX, VVVV, WIG;
2001 SchedWriteFCmpSizes.PS.YMM, SSEPackedSingle, loadv8f32>, TB, VEX, VVVV, VEX_L, WIG;
2004 … SchedWriteFCmpSizes.PD.YMM, SSEPackedDouble, loadv4f64>, TB, PD, VEX, VVVV, VEX_L, WIG;
2008 SchedWriteFCmpSizes.PS.XMM, SSEPackedSingle, memopv4f32>, TB;
2011 SchedWriteFCmpSizes.PD.XMM, SSEPackedDouble, memopv2f64>, TB, PD;
2092 TB, VEX, VVVV, WIG;
2096 TB, VEX, VVVV, VEX_L, WIG;
2100 TB, PD, VEX, VVVV, WIG;
2104 TB, PD, VEX, VVVV, VEX_L, WIG;
2109 memopv4f32, SchedWriteFShuffle.XMM, SSEPackedSingle>, TB;
2112 memopv2f64, SchedWriteFShuffle.XMM, SSEPackedDouble, 1>, TB, PD;
2142 SchedWriteFShuffle.XMM, SSEPackedSingle>, TB, VEX, VVVV, WIG;
2145 SchedWriteFShuffle.XMM, SSEPackedDouble, 1>, TB, PD, VEX, VVVV, WIG;
2148 SchedWriteFShuffle.XMM, SSEPackedSingle>, TB, VEX, VVVV, WIG;
2151 SchedWriteFShuffle.XMM, SSEPackedDouble>, TB, PD, VEX, VVVV, WIG;
2155 SchedWriteFShuffle.YMM, SSEPackedSingle>, TB, VEX, VVVV, VEX_L, WIG;
2158 SchedWriteFShuffle.YMM, SSEPackedDouble>, TB, PD, VEX, VVVV, VEX_L, WIG;
2161 SchedWriteFShuffle.YMM, SSEPackedSingle>, TB, VEX, VVVV, VEX_L, WIG;
2164 SchedWriteFShuffle.YMM, SSEPackedDouble>, TB, PD, VEX, VVVV, VEX_L, WIG;
2170 SchedWriteFShuffle.XMM, SSEPackedSingle>, TB;
2173 SchedWriteFShuffle.XMM, SSEPackedDouble, 1>, TB, PD;
2176 SchedWriteFShuffle.XMM, SSEPackedSingle>, TB;
2179 SchedWriteFShuffle.XMM, SSEPackedDouble>, TB, PD;
2224 SSEPackedSingle>, TB, VEX, WIG;
2226 SSEPackedDouble>, TB, PD, VEX, WIG;
2228 SSEPackedSingle>, TB, VEX, VEX_L, WIG;
2230 SSEPackedDouble>, TB, PD, VEX, VEX_L, WIG;
2244 SSEPackedSingle>, TB;
2246 SSEPackedDouble>, TB, PD;
2328 [], [], 0>, TB, VEX, VVVV, VEX_L, WIG;
2332 [], [], 0>, TB, PD, VEX, VVVV, VEX_L, WIG;
2336 [], [], 0>, TB, VEX, VVVV, WIG;
2340 [], [], 0>, TB, PD, VEX, VVVV, WIG;
2346 [], []>, TB;
2350 [], []>, TB, PD;
2652 SSEPackedSingle, sched.PS.XMM, 0>, TB, VEX, VVVV, WIG;
2655 SSEPackedDouble, sched.PD.XMM, 0>, TB, PD, VEX, VVVV, WIG;
2659 SSEPackedSingle, sched.PS.YMM, 0>, TB, VEX, VVVV, VEX_L, WIG;
2662 SSEPackedDouble, sched.PD.YMM, 0>, TB, PD, VEX, VVVV, VEX_L, WIG;
2668 sched.PS.XMM>, TB;
2671 sched.PD.XMM>, TB, PD;
2681 TB, XS, VEX, VVVV, VEX_LIG, WIG;
2684 TB, XD, VEX, VVVV, VEX_LIG, WIG;
2689 sched.PS.Scl>, TB, XS;
2692 sched.PD.Scl>, TB, XD;
2703 SSEPackedSingle, sched.PS.Scl, 0>, TB, XS, VEX, VVVV, VEX_LIG, WIG;
2706 SSEPackedDouble, sched.PD.Scl, 0>, TB, XD, VEX, VVVV, VEX_LIG, WIG;
2711 SSEPackedSingle, sched.PS.Scl>, TB, XS;
2714 SSEPackedDouble, sched.PD.Scl>, TB, XD;
3032 UseSSE1>, TB, XS;
3036 TB, XS, VEX, VVVV, VEX_LIG, WIG;
3042 ssmem, OpNode, SSEPackedSingle, sched.Scl, UseSSE1>, TB, XS;
3045 TB, XS, VEX, VVVV, VEX_LIG, WIG;
3051 sdmem, OpNode, SSEPackedDouble, sched.Scl, UseSSE2>, TB, XD;
3054 TB, XD, VEX, VVVV, VEX_LIG, WIG;
3181 TB, Requires<[HasSSE2]>;
3185 TB, Requires<[HasSSE2]>;
3228 "prefetcht0\t$src", [(prefetch addr:$src, timm, (i32 3), (i32 1))]>, TB;
3230 "prefetcht1\t$src", [(prefetch addr:$src, timm, (i32 2), (i32 1))]>, TB;
3232 "prefetcht2\t$src", [(prefetch addr:$src, timm, (i32 1), (i32 1))]>, TB;
3234 "prefetchnta\t$src", [(prefetch addr:$src, timm, (i32 0), (i32 1))]>, TB;
3242 TB, Requires<[HasCLFLUSH]>;
3257 TB, Requires<[HasSSE1]>;
3259 TB, Requires<[HasSSE2]>;
3261 TB, Requires<[HasMFence]>;
3282 TB, Sched<[WriteLDMXCSR]>;
3286 TB, Sched<[WriteSTMXCSR]>;
3343 TB, XS, VEX, WIG;
3347 TB, XS, VEX, VEX_L, WIG;
3363 Sched<[SchedWriteVecMoveLS.XMM.MR]>, TB, XS, VEX, WIG;
3366 Sched<[SchedWriteVecMoveLS.YMM.MR]>, TB, XS, VEX, VEX_L, WIG;
3376 TB, XS, Requires<[UseSSE2]>;
3386 TB, XS, Requires<[UseSSE2]>;
3398 TB, XS, Requires<[UseSSE2]>;
3409 TB, XS, Requires<[UseSSE2]>;
3773 SchedWriteShuffle, NoVLX>, TB, PD;
3775 SchedWriteShuffle, NoVLX_Or_NoBWI>, TB, XS;
3777 SchedWriteShuffle, NoVLX_Or_NoBWI>, TB, XD;
4020 TB, PD, VEX, WIG, Sched<[WriteVecExtract]>;
4030 defm VPINSRW : sse2_pinsrw<0>, TB, PD, VEX, VVVV, WIG;
4033 defm PINSRW : sse2_pinsrw, TB, PD;
4322 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, TB, XS,
4328 TB, XS, Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4385 TB, XS, VEX, Requires<[UseAVX]>, WIG;
4389 TB, XS, Requires<[UseSSE2]>;
4579 TB, XD, VEX, VVVV, WIG;
4582 TB, XD, VEX, VVVV, VEX_L, WIG;
4587 TB, PD, VEX, VVVV, WIG;
4590 TB, PD, VEX, VVVV, VEX_L, WIG;
4596 SchedWriteFAddSizes.PS.XMM, memopv4f32>, TB, XD;
4599 SchedWriteFAddSizes.PD.XMM, memopv2f64>, TB, PD;
4987 TB, Requires<[HasSSE3, Not64BitMode]>;
4990 TB, Requires<[HasSSE3, In64BitMode]>;
4994 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
7030 TB, PD, Sched<[SchedWriteVecALU.XMM]>;
7036 TB, PD, Sched<[SchedWriteVecALU.XMM]>;
7043 TB, XD, Sched<[SchedWriteVecALU.XMM]>;
7049 TB, XD, Sched<[SchedWriteVecALU.XMM]>;
7057 "movntss\t{$src, $dst|$dst, $src}", []>, TB, XS;
7060 "movntsd\t{$src, $dst|$dst, $src}", []>, TB, XD;
7475 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L,
7480 [(int_x86_avx_vzeroupper)]>, TB, VEX,