Lines Matching +full:64 +full:mib
75 cl::init(64), cl::Hidden);
217 // Arithmetic with just 32-bit and 64-bit variants and no immediates. in isDataInvariant()
587 MemBytes = 64; in isFrameLoadOpcode()
683 MemBytes = 64; in isFrameStoreOpcode()
1077 // size, others 32/64 bit ops would test higher bits which test16rr don't in findRedundantFlagInstr()
1175 // type (32-bit or 64-bit) we may just need to forbid SP. in classifyLEAReg()
1187 // another we need to add 64-bit registers to the final MI. in classifyLEAReg()
1192 NewSrc = getX86SubSuperRegister(SrcReg, 64); in classifyLEAReg()
1196 // Virtual register of the wrong class, we have to create a temporary 64-bit in classifyLEAReg()
1257 // But testing has shown this *does* help performance in 64-bit mode (at in convertToThreeAddressWithLEA()
1276 MachineInstrBuilder MIB = in convertToThreeAddressWithLEA() local
1284 MIB.addReg(0) in convertToThreeAddressWithLEA()
1293 addRegOffset(MIB, InRegLEA, true, 1); in convertToThreeAddressWithLEA()
1297 addRegOffset(MIB, InRegLEA, true, -1); in convertToThreeAddressWithLEA()
1303 addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm()); in convertToThreeAddressWithLEA()
1315 addRegReg(MIB, InRegLEA, true, InRegLEA, false); in convertToThreeAddressWithLEA()
1323 ImpDef2 = BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), in convertToThreeAddressWithLEA()
1325 InsMI2 = BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY)) in convertToThreeAddressWithLEA()
1328 addRegReg(MIB, InRegLEA, true, InRegLEA2, true); in convertToThreeAddressWithLEA()
1336 MachineInstr *NewMI = MIB; in convertToThreeAddressWithLEA()
1475 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)) in convertToThreeAddress() local
1483 MIB.add(ImplicitOp); in convertToThreeAddress()
1484 NewMI = MIB; in convertToThreeAddress()
1513 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)) in convertToThreeAddress() local
1517 MIB.add(ImplicitOp); in convertToThreeAddress()
1519 NewMI = addOffset(MIB, 1); in convertToThreeAddress()
1539 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)) in convertToThreeAddress() local
1543 MIB.add(ImplicitOp); in convertToThreeAddress()
1545 NewMI = addOffset(MIB, -1); in convertToThreeAddress()
1590 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest); in convertToThreeAddress() local
1592 MIB.add(ImplicitOp); in convertToThreeAddress()
1594 MIB.add(ImplicitOp2); in convertToThreeAddress()
1596 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2); in convertToThreeAddress()
1633 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)) in convertToThreeAddress() local
1637 MIB.add(ImplicitOp); in convertToThreeAddress()
1639 NewMI = addOffset(MIB, MI.getOperand(2)); in convertToThreeAddress()
1673 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)) in convertToThreeAddress() local
1677 MIB.add(ImplicitOp); in convertToThreeAddress()
1679 NewMI = addOffset(MIB, -Imm); in convertToThreeAddress()
1696 MachineInstrBuilder MIB = in convertToThreeAddress() local
1698 NewMI = addOffset(MIB, -Imm); in convertToThreeAddress()
2330 FROM_TO_SIZE(SHRD64rri8, SHLD64rri8, 64) in commuteInstructionImpl()
2501 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0] in commuteInstructionImpl()
2502 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0] in commuteInstructionImpl()
3711 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc)); in replaceBranchWithTailCall() local
3712 MIB->addOperand(TailCall.getOperand(0)); // Destination. in replaceBranchWithTailCall()
3713 MIB.addImm(0); // Stack offset (not used). in replaceBranchWithTailCall()
3714 MIB->addOperand(BranchCond[0]); // Condition. in replaceBranchWithTailCall()
3715 MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters. in replaceBranchWithTailCall()
3722 LiveRegs.stepForward(*MIB, Clobbers); in replaceBranchWithTailCall()
3724 MIB.addReg(C.first, RegState::Implicit); in replaceBranchWithTailCall()
3725 MIB.addReg(C.first, RegState::Implicit | RegState::Define); in replaceBranchWithTailCall()
4118 // We have cmov instructions for 16, 32, and 64 bit general purpose registers. in canInsertSelect()
4254 // Copying to or from a physical H register on x86-64 requires a NOREX in copyPhysReg()
4367 // Copying to or from a physical H register on x86-64 requires a NOREX in getLoadStoreRegOpcode()
4471 case 64: in getLoadStoreRegOpcode()
4472 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass"); in getLoadStoreRegOpcode()
4551 // instruction. It is quite common for x86-64. in getConstValDefinedInReg()
4553 // We use following pattern to setup 64b immediate. in getConstValDefinedInReg()
4695 BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64); in loadStoreTileReg()
4709 BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64); in loadStoreTileReg()
4921 // "ELF Handling for Thread-Local Storage" specifies that x86-64 GOTTPOFF, and in isDefConvertible()
5703 // 64 bit operations accept sign extended 32 bit immediates. in foldImmediateImpl()
5875 static bool Expand2AddrUndef(MachineInstrBuilder &MIB, in Expand2AddrUndef() argument
5878 Register Reg = MIB.getReg(0); in Expand2AddrUndef()
5879 MIB->setDesc(Desc); in Expand2AddrUndef()
5883 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); in Expand2AddrUndef()
5885 assert(MIB.getReg(1) == Reg && MIB.getReg(2) == Reg && "Misplaced operand"); in Expand2AddrUndef()
5895 static bool Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, in Expand2AddrKreg() argument
5898 MIB->setDesc(Desc); in Expand2AddrKreg()
5899 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); in Expand2AddrKreg()
5903 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII, in expandMOV32r1() argument
5905 MachineBasicBlock &MBB = *MIB->getParent(); in expandMOV32r1()
5906 const DebugLoc &DL = MIB->getDebugLoc(); in expandMOV32r1()
5907 Register Reg = MIB.getReg(0); in expandMOV32r1()
5910 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg) in expandMOV32r1()
5915 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r)); in expandMOV32r1()
5916 MIB.addReg(Reg); in expandMOV32r1()
5921 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB, in ExpandMOVImmSExti8() argument
5924 MachineBasicBlock &MBB = *MIB->getParent(); in ExpandMOVImmSExti8()
5925 const DebugLoc &DL = MIB->getDebugLoc(); in ExpandMOVImmSExti8()
5926 int64_t Imm = MIB->getOperand(1).getImm(); in ExpandMOVImmSExti8()
5928 MachineBasicBlock::iterator I = MIB.getInstr(); in ExpandMOVImmSExti8()
5933 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 || in ExpandMOVImmSExti8()
5934 MIB->getOpcode() == X86::MOV32ImmSExti8); in ExpandMOVImmSExti8()
5940 MIB->setDesc(TII.get(MIB->getOpcode() == X86::MOV32ImmSExti8 in ExpandMOVImmSExti8()
5946 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and in ExpandMOVImmSExti8()
5950 MIB->setDesc(TII.get(X86::POP64r)); in ExpandMOVImmSExti8()
5951 MIB->getOperand(0).setReg(getX86SubSuperRegister(MIB.getReg(0), 64)); in ExpandMOVImmSExti8()
5953 assert(MIB->getOpcode() == X86::MOV32ImmSExti8); in ExpandMOVImmSExti8()
5956 MIB->setDesc(TII.get(X86::POP32r)); in ExpandMOVImmSExti8()
5958 MIB->removeOperand(1); in ExpandMOVImmSExti8()
5959 MIB->addImplicitDefUseOperands(*MBB.getParent()); in ExpandMOVImmSExti8()
5979 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5981 static void expandLoadStackGuard(MachineInstrBuilder &MIB, in expandLoadStackGuard() argument
5983 MachineBasicBlock &MBB = *MIB->getParent(); in expandLoadStackGuard()
5984 const DebugLoc &DL = MIB->getDebugLoc(); in expandLoadStackGuard()
5985 Register Reg = MIB.getReg(0); in expandLoadStackGuard()
5987 cast<GlobalValue>((*MIB->memoperands_begin())->getValue()); in expandLoadStackGuard()
5993 MachineBasicBlock::iterator I = MIB.getInstr(); in expandLoadStackGuard()
6002 MIB->setDebugLoc(DL); in expandLoadStackGuard()
6003 MIB->setDesc(TII.get(X86::MOV64rm)); in expandLoadStackGuard()
6004 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0); in expandLoadStackGuard()
6007 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) { in expandXorFP() argument
6008 MachineBasicBlock &MBB = *MIB->getParent(); in expandXorFP()
6013 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr; in expandXorFP()
6014 MIB->setDesc(TII.get(XorOp)); in expandXorFP()
6015 MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef); in expandXorFP()
6022 static bool expandNOVLXLoad(MachineInstrBuilder &MIB, in expandNOVLXLoad() argument
6026 Register DestReg = MIB.getReg(0); in expandNOVLXLoad()
6030 MIB->setDesc(LoadDesc); in expandNOVLXLoad()
6033 MIB->setDesc(BroadcastDesc); in expandNOVLXLoad()
6036 MIB->getOperand(0).setReg(DestReg); in expandNOVLXLoad()
6044 static bool expandNOVLXStore(MachineInstrBuilder &MIB, in expandNOVLXStore() argument
6048 Register SrcReg = MIB.getReg(X86::AddrNumOperands); in expandNOVLXStore()
6052 MIB->setDesc(StoreDesc); in expandNOVLXStore()
6055 MIB->setDesc(ExtractDesc); in expandNOVLXStore()
6058 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg); in expandNOVLXStore()
6059 MIB.addImm(0x0); // Append immediate to extract from the lower bits. in expandNOVLXStore()
6065 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) { in expandSHXDROT() argument
6066 MIB->setDesc(Desc); in expandSHXDROT()
6067 int64_t ShiftAmt = MIB->getOperand(2).getImm(); in expandSHXDROT()
6069 MIB->removeOperand(2); in expandSHXDROT()
6071 MIB.addReg(MIB.getReg(1), getUndefRegState(MIB->getOperand(1).isUndef())); in expandSHXDROT()
6073 MIB.addImm(ShiftAmt); in expandSHXDROT()
6079 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); in expandPostRAPseudo() local
6082 return Expand2AddrUndef(MIB, get(X86::XOR32rr)); in expandPostRAPseudo()
6084 return expandMOV32r1(MIB, *this, /*MinusOne=*/false); in expandPostRAPseudo()
6086 return expandMOV32r1(MIB, *this, /*MinusOne=*/true); in expandPostRAPseudo()
6089 return ExpandMOVImmSExti8(MIB, *this, Subtarget); in expandPostRAPseudo()
6091 return Expand2AddrUndef(MIB, get(X86::SBB32rr)); in expandPostRAPseudo()
6093 return Expand2AddrUndef(MIB, get(X86::SBB64rr)); in expandPostRAPseudo()
6095 return Expand2AddrUndef(MIB, get(X86::MMX_PXORrr)); in expandPostRAPseudo()
6101 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr)); in expandPostRAPseudo()
6105 Register SrcReg = MIB.getReg(0); in expandPostRAPseudo()
6107 MIB->getOperand(0).setReg(XReg); in expandPostRAPseudo()
6108 Expand2AddrUndef(MIB, get(X86::VXORPSrr)); in expandPostRAPseudo()
6109 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
6118 Register SrcReg = MIB.getReg(0); in expandPostRAPseudo()
6121 return Expand2AddrUndef(MIB, in expandPostRAPseudo()
6126 MIB->getOperand(0).setReg(SrcReg); in expandPostRAPseudo()
6127 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); in expandPostRAPseudo()
6132 Register SrcReg = MIB.getReg(0); in expandPostRAPseudo()
6136 MIB->getOperand(0).setReg(XReg); in expandPostRAPseudo()
6137 Expand2AddrUndef(MIB, get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr)); in expandPostRAPseudo()
6138 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
6145 MIB->getOperand(0).setReg(ZReg); in expandPostRAPseudo()
6147 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); in expandPostRAPseudo()
6150 return Expand2AddrUndef(MIB, in expandPostRAPseudo()
6153 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr)); in expandPostRAPseudo()
6155 Register Reg = MIB.getReg(0); in expandPostRAPseudo()
6157 MIB->setDesc(get(X86::VCMPPSYrri)); in expandPostRAPseudo()
6158 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf); in expandPostRAPseudo()
6162 Register Reg = MIB.getReg(0); in expandPostRAPseudo()
6163 MIB->setDesc(get(X86::VPTERNLOGDZrri)); in expandPostRAPseudo()
6166 MIB.addReg(Reg, RegState::Undef) in expandPostRAPseudo()
6174 Register Reg = MIB.getReg(0); in expandPostRAPseudo()
6175 Register MaskReg = MIB.getReg(1); in expandPostRAPseudo()
6176 unsigned MaskState = getRegState(MIB->getOperand(1)); in expandPostRAPseudo()
6181 MIB->setDesc(get(Opc)); in expandPostRAPseudo()
6184 MIB.addReg(Reg, RegState::Undef) in expandPostRAPseudo()
6192 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm), in expandPostRAPseudo()
6195 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm), in expandPostRAPseudo()
6198 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm), in expandPostRAPseudo()
6201 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm), in expandPostRAPseudo()
6204 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr), in expandPostRAPseudo()
6207 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr), in expandPostRAPseudo()
6210 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr), in expandPostRAPseudo()
6213 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr), in expandPostRAPseudo()
6216 Register Reg = MIB.getReg(0); in expandPostRAPseudo()
6219 MIB->getOperand(0).setReg(Reg32); in expandPostRAPseudo()
6220 MIB.addReg(Reg, RegState::ImplicitDefine); in expandPostRAPseudo()
6227 MachineBasicBlock &MBB = *MIB->getParent(); in expandPostRAPseudo()
6229 MachineInstr *NewMI = BuildMI(MBB, MI, MIB->getDebugLoc(), in expandPostRAPseudo()
6244 MIB->setDesc(get(Is64Bit ? X86::POP64r : X86::POP32r)); in expandPostRAPseudo()
6251 MachineBasicBlock &MBB = *MIB->getParent(); in expandPostRAPseudo()
6253 BuildMI(MBB, MI, MIB->getDebugLoc(), in expandPostRAPseudo()
6256 BuildMI(MBB, MI, MIB->getDebugLoc(), in expandPostRAPseudo()
6270 return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0); in expandPostRAPseudo()
6272 return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0); in expandPostRAPseudo()
6274 return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0); in expandPostRAPseudo()
6276 return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0); in expandPostRAPseudo()
6278 return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0); in expandPostRAPseudo()
6280 return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0); in expandPostRAPseudo()
6282 expandLoadStackGuard(MIB, *this); in expandPostRAPseudo()
6286 return expandXorFP(MIB, *this); in expandPostRAPseudo()
6288 return expandSHXDROT(MIB, get(X86::SHLD32rri8)); in expandPostRAPseudo()
6290 return expandSHXDROT(MIB, get(X86::SHLD64rri8)); in expandPostRAPseudo()
6292 return expandSHXDROT(MIB, get(X86::SHRD32rri8)); in expandPostRAPseudo()
6294 return expandSHXDROT(MIB, get(X86::SHRD64rri8)); in expandPostRAPseudo()
6296 MIB->setDesc(get(X86::OR8rr)); in expandPostRAPseudo()
6299 MIB->setDesc(get(X86::OR16rr)); in expandPostRAPseudo()
6302 MIB->setDesc(get(X86::OR32rr)); in expandPostRAPseudo()
6305 MIB->setDesc(get(X86::OR64rr)); in expandPostRAPseudo()
6308 MIB->setDesc(get(X86::OR8ri)); in expandPostRAPseudo()
6311 MIB->setDesc(get(X86::OR16ri)); in expandPostRAPseudo()
6314 MIB->setDesc(get(X86::OR32ri)); in expandPostRAPseudo()
6317 MIB->setDesc(get(X86::OR64ri32)); in expandPostRAPseudo()
6324 /// the first 32 or 64-bits of the destination register and leave the rest
7095 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs, in addOperands() argument
7102 MIB.add(MOs[i]); in addOperands()
7103 addOffset(MIB, PtrOffset); in addOperands()
7111 MIB.addDisp(MO, PtrOffset); in addOperands()
7113 MIB.add(MO); in addOperands()
7154 MachineInstrBuilder MIB(MF, NewMI); in fuseTwoAddrInst() local
7155 addOperands(MIB, MOs); in fuseTwoAddrInst()
7161 MIB.add(MO); in fuseTwoAddrInst()
7164 MIB.add(MO); in fuseTwoAddrInst()
7171 return MIB; in fuseTwoAddrInst()
7182 MachineInstrBuilder MIB(MF, NewMI); in fuseInst() local
7188 addOperands(MIB, MOs, PtrOffset); in fuseInst()
7190 MIB.add(MO); in fuseInst()
7203 return MIB; in fuseInst()
7210 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt, in makeM0Inst() local
7212 addOperands(MIB, MOs); in makeM0Inst()
7213 return MIB.addImm(0); in makeM0Inst()
7253 // Move the upper 64-bits of the second operand to the lower 64-bits. in foldMemoryOperandCustom()
7417 // If this is a 64-bit load, but the spill slot is 32, then we can do in foldMemoryOperandImpl()
7489 // MOV32r0 is special b/c it's used to clear a 64-bit register too. in foldMemoryOperandImpl()
7750 RegSize > 64) { in isNonFoldablePartialRegisterLoad()
7751 // These instructions only load 64 bits, we can't fold them if the in isNonFoldablePartialRegisterLoad()
7752 // destination register is wider than 64 bits (8 bytes), and its user in isNonFoldablePartialRegisterLoad()
8026 Alignment = Align(64); in foldMemoryOperandImpl()
8223 FOLD_BROADCAST(64); in foldMemoryOperandImpl()
8317 assert((SpillSize == 64 || STI.hasVLX()) && in getBroadcastOpcode()
8318 "Can't broadcast less than 64 bytes without AVX512VL!"); in getBroadcastOpcode()
8329 case 64: \ in getBroadcastOpcode()
8410 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg); in unfoldMemoryOperand() local
8412 MIB.add(AddrOp); in unfoldMemoryOperand()
8413 MIB.setMemRefs(MMOs); in unfoldMemoryOperand()
8414 NewMIs.push_back(MIB); in unfoldMemoryOperand()
8428 MachineInstrBuilder MIB(MF, DataMI); in unfoldMemoryOperand() local
8431 MIB.addReg(Reg, RegState::Define); in unfoldMemoryOperand()
8433 MIB.add(BeforeOp); in unfoldMemoryOperand()
8435 MIB.addReg(Reg); in unfoldMemoryOperand()
8437 MIB.add(AfterOp); in unfoldMemoryOperand()
8439 MIB.addReg(ImpOp.getReg(), getDefRegState(ImpOp.isDef()) | in unfoldMemoryOperand()
8488 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); in unfoldMemoryOperand() local
8490 MIB.add(AddrOp); in unfoldMemoryOperand()
8491 MIB.addReg(Reg, RegState::Kill); in unfoldMemoryOperand()
8492 MIB.setMemRefs(MMOs); in unfoldMemoryOperand()
8493 NewMIs.push_back(MIB); in unfoldMemoryOperand()
8781 if ((Offset2 - Offset1) / 8 > 64) in shouldScheduleLoadsNear()
8803 // XMM registers. In 64-bit mode we can be a bit more aggressive since we in shouldScheduleLoadsNear()
10019 // We may need to describe a 64-bit parameter with a 32-bit LEA. in describeLoadedValue()
10101 // 64-bit parameters, so we need to consider super-registers. in describeLoadedValue()
10111 // 64-bit parameters are zero-materialized using XOR32rr, so also consider in describeLoadedValue()
10137 Expr = DIExpression::appendExt(Expr, 32, 64, true); in describeLoadedValue()
10628 // upper bits of a 64-bit register automagically. in buildClearRegister()