Lines Matching +full:0 +full:xd9
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
91 // ST(0) = ST(0) + [mem]
128 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
131 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
133 // ST(0) = ST(0) + [memint]
177 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
180 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
198 defm SUBR: FPBinary<any_fsub ,MRM5m, "subr", 0>;
207 defm DIVR: FPBinary<any_fdiv, MRM7m, "divr", 0>;
212 : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>;
214 : FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>;
216 : FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>;
258 def _F : FPI<0xD9, fp, (outs), (ins), asmstring>;
271 let hasSideEffects = 0 in {
277 def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">;
285 def XAM_F : FPI<0xD9, MRM_E5, (outs), (ins), "fxam">;
292 def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">;
293 def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">;
295 def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">;
296 def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">;
298 def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">;
299 def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">;
301 def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">;
302 def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">;
307 def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins anymem:$src), "frstor\t$src">;
309 def FLDENVm : I<0xD9, MRM4m, (outs), (ins anymem:$src), "fldenv\t$src",
314 def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins anymem:$dst), "fnsave\t$dst">;
316 def FSTENVm : I<0xD9, MRM6m, (outs), (ins anymem:$dst), "fnstenv\t$dst",
321 def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">;
324 def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">;
326 def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">;
365 def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op),
367 def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op),
369 def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op),
371 def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RSTi:$op),
373 def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op),
375 def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op),
377 def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op),
379 def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op),
401 let mayRaiseFPException = 0 in {
420 } // mayRaiseFPException = 0
436 let mayStore = 1, hasSideEffects = 0 in {
447 let mayStore = 1, hasSideEffects = 0 in {
467 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
468 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
469 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
470 let mayRaiseFPException = 0 in {
471 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
472 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
473 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
477 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
478 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
479 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
480 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
481 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
482 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
483 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
484 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
485 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
486 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
512 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
513 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
514 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
519 def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">;
520 def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">;
521 def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">;
522 let mayRaiseFPException = 0 in
523 def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">;
542 let SchedRW = [WriteFLD0], Uses = [FPCW], mayRaiseFPException = 0 in
543 def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">;
545 let SchedRW = [WriteFLD1], Uses = [FPCW], mayRaiseFPException = 0 in
546 def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">;
548 let SchedRW = [WriteFLDC], Defs = [FPSW], Uses = [FPCW], mayRaiseFPException = 0 in {
549 def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>;
550 def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>;
551 def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>;
552 def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>;
553 def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>;
557 let SchedRW = [WriteFCom], Uses = [FPCW], hasSideEffects = 0 in {
568 // CC = ST(0) cmp ST(i)
591 def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i)
593 def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop
595 def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop
600 def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i)
602 def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop
605 def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg),
607 def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg),
614 let Defs = [AX, FPSW], Uses = [FPSW], hasSideEffects = 0 in
615 def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags
618 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
623 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
630 def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">;
631 def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">;
634 def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>;
637 def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>;
642 def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>;
646 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
647 def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>;
648 def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>;
650 def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>;
651 def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>;
652 def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>;
653 def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>;
654 def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>;
655 def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>;
656 def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>;
657 def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>;
658 def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>;
659 def FCOS : I<0xD9, MRM_FF, (outs), (ins), "fcos", []>;
660 def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>;
661 def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>;
662 def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>;
663 def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>;
668 def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst),
671 def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst),
677 def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src),
680 def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src),