Lines Matching refs:TB
41 TB, OpSize16, Sched<[WriteALU]>;
45 TB, OpSize16, Sched<[WriteLoad]>;
49 [(set GR32:$dst, (sext GR8:$src))]>, TB,
53 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB,
57 [(set GR32:$dst, (sext GR16:$src))]>, TB,
62 OpSize32, TB, Sched<[WriteLoad]>;
67 TB, OpSize16, Sched<[WriteALU]>;
71 TB, OpSize16, Sched<[WriteLoad]>;
75 [(set GR32:$dst, (zext GR8:$src))]>, TB,
79 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB,
83 [(set GR32:$dst, (zext GR16:$src))]>, TB,
88 TB, OpSize32, Sched<[WriteLoad]>;
96 []>, TB, OpSize16, Sched<[WriteALU]>;
99 []>, TB, OpSize16, Sched<[WriteALU]>;
103 []>, OpSize16, TB, Sched<[WriteLoad]>;
106 []>, TB, OpSize16, Sched<[WriteLoad]>;
117 []>, TB, OpSize32, Sched<[WriteALU]>;
122 []>, TB, OpSize32, Sched<[WriteLoad]>;
127 []>, TB, OpSize32, Sched<[WriteALU]>;
132 []>, TB, OpSize32, Sched<[WriteLoad]>;
141 [(set GR64:$dst, (sext GR8:$src))]>, TB,
146 TB, Sched<[WriteLoad]>;
149 [(set GR64:$dst, (sext GR16:$src))]>, TB,
154 TB, Sched<[WriteLoad]>;
188 TB, Sched<[WriteALU]>;
192 TB, Sched<[WriteLoad]>;
195 TB, Sched<[WriteALU]>;
199 TB, Sched<[WriteLoad]>;