Lines Matching full:src2
706 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
708 "{$src2, $dst|$dst, $src2}"),
709 [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK;
713 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
715 "{$src2, $dst|$dst, $src2}"),
716 [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>,
721 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
723 "{$src2, $dst|$dst, $src2}"),
724 [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>,
729 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
731 "{$src2, $dst|$dst, $src2}"),
732 [(set EFLAGS, (Op addr:$dst, GR64:$src2))]>, LOCK;
738 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
740 "{$src2, $dst|$dst, $src2}"),
741 [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))]>,
746 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
748 "{$src2, $dst|$dst, $src2}"),
749 [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))]>,
754 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
756 "{$src2, $dst|$dst, $src2}"),
757 [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))]>,
762 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
764 "{$src2, $dst|$dst, $src2}"),
765 [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))]>, LOCK;
769 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
771 "{$src2, $dst|$dst, $src2}"),
772 [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))]>,
777 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
779 "{$src2, $dst|$dst, $src2}"),
780 [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))]>,
785 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
787 "{$src2, $dst|$dst, $src2}"),
788 [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))]>,
882 def 16m : Ii8<0xBA, Form, (outs), (ins i16mem:$src1, i8imm:$src2),
883 !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"),
884 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 16)))]>,
886 def 32m : Ii8<0xBA, Form, (outs), (ins i32mem:$src1, i8imm:$src2),
887 !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"),
888 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 32)))]>,
890 def 64m : RIi8<0xBA, Form, (outs), (ins i64mem:$src1, i8imm:$src2),
891 !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"),
892 [(set EFLAGS, (!cast<SDNode>("x86" # s) addr:$src1, timm:$src2, (i32 64)))]>,
900 def 16rm : I<Opc8, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
901 !strconcat(s, "{w}\t{$src2, $src1|$src1, $src2}"),
902 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR16:$src2))]>,
904 def 32rm : I<Opc8, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
905 !strconcat(s, "{l}\t{$src2, $src1|$src1, $src2}"),
906 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR32:$src2))]>,
908 def 64rm : RI<Opc8, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
909 !strconcat(s, "{q}\t{$src2, $src1|$src1, $src2}"),
910 [(set EFLAGS, (!cast<SDNode>("x86_rm_" # s) addr:$src1, GR64:$src2))]>,
1108 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))),
1109 (!cast<Instruction>(Name#"SSrm") FR32:$src1, addr:$src2)>,
1111 def : Pat<(op FR32:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))),
1112 (!cast<Instruction>("V"#Name#"SSrm") FR32:$src1, addr:$src2)>,
1114 def : Pat<(op FR32X:$src1, (bitconvert (i32 (atomic_load_32 addr:$src2)))),
1115 (!cast<Instruction>("V"#Name#"SSZrm") FR32X:$src1, addr:$src2)>,
1118 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))),
1119 (!cast<Instruction>(Name#"SDrm") FR64:$src1, addr:$src2)>,
1121 def : Pat<(op FR64:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))),
1122 (!cast<Instruction>("V"#Name#"SDrm") FR64:$src1, addr:$src2)>,
1124 def : Pat<(op FR64X:$src1, (bitconvert (i64 (atomic_load_64 addr:$src2)))),
1125 (!cast<Instruction>("V"#Name#"SDZrm") FR64X:$src1, addr:$src2)>,
1456 def ADD8rr_DB : I<0, Pseudo, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1458 [(set GR8:$dst, (or_is_add GR8:$src1, GR8:$src2))]>;
1459 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1461 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1462 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1464 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1465 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1467 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1471 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1473 [(set GR8:$dst, (or_is_add GR8:$src1, imm:$src2))]>;
1474 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1476 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1477 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1479 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1481 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1484 i64immSExt32:$src2))]>;
1944 def : Pat<(X86fshl GR16:$src1, GR16:$src2, (shiftMask32 CL)),
1945 (!cast<Instruction>(SHLD16rrCL#suffix) GR16:$src1, GR16:$src2)>;
1946 def : Pat<(X86fshr GR16:$src2, GR16:$src1, (shiftMask32 CL)),
1947 (!cast<Instruction>(SHRD16rrCL#suffix) GR16:$src1, GR16:$src2)>;
1950 def : Pat<(fshl GR32:$src1, GR32:$src2, (shiftMask32 CL)),
1951 (!cast<Instruction>(SHLD32rrCL#suffix) GR32:$src1, GR32:$src2)>;
1952 def : Pat<(fshr GR32:$src2, GR32:$src1, (shiftMask32 CL)),
1953 (!cast<Instruction>(SHRD32rrCL#suffix) GR32:$src1, GR32:$src2)>;
1956 def : Pat<(fshl GR64:$src1, GR64:$src2, (shiftMask64 CL)),
1957 (!cast<Instruction>(SHLD64rrCL#suffix) GR64:$src1, GR64:$src2)>;
1958 def : Pat<(fshr GR64:$src2, GR64:$src1, (shiftMask64 CL)),
1959 (!cast<Instruction>(SHRD64rrCL#suffix) GR64:$src1, GR64:$src2)>;
1969 def : Pat<(and rc:$src1, (rotl -2, GR8:$src2)),
1971 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1972 def : Pat<(or rc:$src1, (shl 1, GR8:$src2)),
1974 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1975 def : Pat<(xor rc:$src1, (shl 1, GR8:$src2)),
1977 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1980 def : Pat<(and rc:$src1, (rotl -2, (mask GR8:$src2))),
1982 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1983 def : Pat<(or rc:$src1, (shl 1, (mask GR8:$src2))),
1985 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1986 def : Pat<(xor rc:$src1, (shl 1, (mask GR8:$src2))),
1988 (INSERT_SUBREG (vt (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
2002 …def : Pat<(add GR8 :$src1, GR8 :$src2), (!cast<Instruction>(ADD8rr#suffix) GR8 :$src1, GR8 :$src2)…
2003 …def : Pat<(add GR16:$src1, GR16:$src2), (!cast<Instruction>(ADD16rr#suffix) GR16:$src1, GR16:$src2…
2004 …def : Pat<(add GR32:$src1, GR32:$src2), (!cast<Instruction>(ADD32rr#suffix) GR32:$src1, GR32:$src2…
2005 …def : Pat<(add GR64:$src1, GR64:$src2), (!cast<Instruction>(ADD64rr#suffix) GR64:$src1, GR64:$src2…
2008 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
2009 (!cast<Instruction>(ADD8rm#suffix) GR8:$src1, addr:$src2)>;
2010 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
2011 (!cast<Instruction>(ADD16rm#suffix) GR16:$src1, addr:$src2)>;
2012 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
2013 (!cast<Instruction>(ADD32rm#suffix) GR32:$src1, addr:$src2)>;
2014 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
2015 (!cast<Instruction>(ADD64rm#suffix) GR64:$src1, addr:$src2)>;
2018 … def : Pat<(add GR8 :$src1, imm:$src2), (!cast<Instruction>(ADD8ri#suffix) GR8:$src1 , imm:$src2)>;
2019 …def : Pat<(add GR16:$src1, imm:$src2), (!cast<Instruction>(ADD16ri#suffix) GR16:$src1, imm:$src2)>;
2020 …def : Pat<(add GR32:$src1, imm:$src2), (!cast<Instruction>(ADD32ri#suffix) GR32:$src1, imm:$src2)>;
2021 …f : Pat<(add GR64:$src1, i64immSExt32:$src2), (!cast<Instruction>(ADD64ri32#suffix) GR64:$src1, i6…
2024 …def : Pat<(sub GR8 :$src1, GR8 :$src2), (!cast<Instruction>(SUB8rr#suffix) GR8 :$src1, GR8 :$src2…
2025 …def : Pat<(sub GR16:$src1, GR16:$src2), (!cast<Instruction>(SUB16rr#suffix) GR16:$src1, GR16:$src2…
2026 …def : Pat<(sub GR32:$src1, GR32:$src2), (!cast<Instruction>(SUB32rr#suffix) GR32:$src1, GR32:$src2…
2027 …def : Pat<(sub GR64:$src1, GR64:$src2), (!cast<Instruction>(SUB64rr#suffix) GR64:$src1, GR64:$src2…
2030 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
2031 (!cast<Instruction>(SUB8rm#suffix) GR8:$src1, addr:$src2)>;
2032 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
2033 (!cast<Instruction>(SUB16rm#suffix) GR16:$src1, addr:$src2)>;
2034 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
2035 (!cast<Instruction>(SUB32rm#suffix) GR32:$src1, addr:$src2)>;
2036 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
2037 (!cast<Instruction>(SUB64rm#suffix) GR64:$src1, addr:$src2)>;
2040 def : Pat<(sub GR8:$src1, imm:$src2),
2041 (!cast<Instruction>(SUB8ri#suffix) GR8:$src1, imm:$src2)>;
2042 def : Pat<(sub GR16:$src1, imm:$src2),
2043 (!cast<Instruction>(SUB16ri#suffix) GR16:$src1, imm:$src2)>;
2044 def : Pat<(sub GR32:$src1, imm:$src2),
2045 (!cast<Instruction>(SUB32ri#suffix) GR32:$src1, imm:$src2)>;
2046 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
2047 (!cast<Instruction>(SUB64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>;
2056 def : Pat<(mul GR16:$src1, GR16:$src2),
2057 (!cast<Instruction>(IMUL16rr#suffix) GR16:$src1, GR16:$src2)>;
2058 def : Pat<(mul GR32:$src1, GR32:$src2),
2059 (!cast<Instruction>(IMUL32rr#suffix) GR32:$src1, GR32:$src2)>;
2060 def : Pat<(mul GR64:$src1, GR64:$src2),
2061 (!cast<Instruction>(IMUL64rr#suffix) GR64:$src1, GR64:$src2)>;
2064 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
2065 (!cast<Instruction>(IMUL16rm#suffix) GR16:$src1, addr:$src2)>;
2066 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
2067 (!cast<Instruction>(IMUL32rm#suffix) GR32:$src1, addr:$src2)>;
2068 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
2069 (!cast<Instruction>(IMUL64rm#suffix) GR64:$src1, addr:$src2)>;
2072 …def : Pat<(or GR8 :$src1, GR8 :$src2), (!cast<Instruction>(OR8rr#suffix) GR8 :$src1, GR8 :$src2)>;
2073 …def : Pat<(or GR16:$src1, GR16:$src2), (!cast<Instruction>(OR16rr#suffix) GR16:$src1, GR16:$src2)>;
2074 …def : Pat<(or GR32:$src1, GR32:$src2), (!cast<Instruction>(OR32rr#suffix) GR32:$src1, GR32:$src2)>;
2075 …def : Pat<(or GR64:$src1, GR64:$src2), (!cast<Instruction>(OR64rr#suffix) GR64:$src1, GR64:$src2)>;
2078 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
2079 (!cast<Instruction>(OR8rm#suffix) GR8:$src1, addr:$src2)>;
2080 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
2081 (!cast<Instruction>(OR16rm#suffix) GR16:$src1, addr:$src2)>;
2082 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
2083 (!cast<Instruction>(OR32rm#suffix) GR32:$src1, addr:$src2)>;
2084 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
2085 (!cast<Instruction>(OR64rm#suffix) GR64:$src1, addr:$src2)>;
2088 … def : Pat<(or GR8:$src1 , imm:$src2), (!cast<Instruction>(OR8ri#suffix) GR8 :$src1, imm:$src2)>;
2089 … def : Pat<(or GR16:$src1, imm:$src2), (!cast<Instruction>(OR16ri#suffix) GR16:$src1, imm:$src2)>;
2090 … def : Pat<(or GR32:$src1, imm:$src2), (!cast<Instruction>(OR32ri#suffix) GR32:$src1, imm:$src2)>;
2091 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
2092 (!cast<Instruction>(OR64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>;
2095 …def : Pat<(xor GR8 :$src1, GR8 :$src2), (!cast<Instruction>(XOR8rr#suffix) GR8 :$src1, GR8 :$src2…
2096 …def : Pat<(xor GR16:$src1, GR16:$src2), (!cast<Instruction>(XOR16rr#suffix) GR16:$src1, GR16:$src2…
2097 …def : Pat<(xor GR32:$src1, GR32:$src2), (!cast<Instruction>(XOR32rr#suffix) GR32:$src1, GR32:$src2…
2098 …def : Pat<(xor GR64:$src1, GR64:$src2), (!cast<Instruction>(XOR64rr#suffix) GR64:$src1, GR64:$src2…
2101 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
2102 (!cast<Instruction>(XOR8rm#suffix) GR8:$src1, addr:$src2)>;
2103 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
2104 (!cast<Instruction>(XOR16rm#suffix) GR16:$src1, addr:$src2)>;
2105 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
2106 (!cast<Instruction>(XOR32rm#suffix) GR32:$src1, addr:$src2)>;
2107 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
2108 (!cast<Instruction>(XOR64rm#suffix) GR64:$src1, addr:$src2)>;
2111 def : Pat<(xor GR8:$src1, imm:$src2),
2112 (!cast<Instruction>(XOR8ri#suffix) GR8:$src1, imm:$src2)>;
2113 def : Pat<(xor GR16:$src1, imm:$src2),
2114 (!cast<Instruction>(XOR16ri#suffix) GR16:$src1, imm:$src2)>;
2115 def : Pat<(xor GR32:$src1, imm:$src2),
2116 (!cast<Instruction>(XOR32ri#suffix) GR32:$src1, imm:$src2)>;
2117 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
2118 (!cast<Instruction>(XOR64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>;
2121 …def : Pat<(and GR8 :$src1, GR8 :$src2), (!cast<Instruction>(AND8rr#suffix) GR8 :$src1, GR8 :$src2…
2122 …def : Pat<(and GR16:$src1, GR16:$src2), (!cast<Instruction>(AND16rr#suffix) GR16:$src1, GR16:$src2…
2123 …def : Pat<(and GR32:$src1, GR32:$src2), (!cast<Instruction>(AND32rr#suffix) GR32:$src1, GR32:$src2…
2124 …def : Pat<(and GR64:$src1, GR64:$src2), (!cast<Instruction>(AND64rr#suffix) GR64:$src1, GR64:$src2…
2127 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
2128 (!cast<Instruction>(AND8rm#suffix) GR8:$src1, addr:$src2)>;
2129 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
2130 (!cast<Instruction>(AND16rm#suffix) GR16:$src1, addr:$src2)>;
2131 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
2132 (!cast<Instruction>(AND32rm#suffix) GR32:$src1, addr:$src2)>;
2133 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
2134 (!cast<Instruction>(AND64rm#suffix) GR64:$src1, addr:$src2)>;
2137 def : Pat<(and GR8:$src1, imm:$src2),
2138 (!cast<Instruction>(AND8ri#suffix) GR8:$src1, imm:$src2)>;
2139 def : Pat<(and GR16:$src1, imm:$src2),
2140 (!cast<Instruction>(AND16ri#suffix) GR16:$src1, imm:$src2)>;
2141 def : Pat<(and GR32:$src1, imm:$src2),
2142 (!cast<Instruction>(AND32ri#suffix) GR32:$src1, imm:$src2)>;
2143 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
2144 (!cast<Instruction>(AND64ri32#suffix) GR64:$src1, i64immSExt32:$src2)>;
2179 def : Pat<(mul GR16:$src1, imm:$src2),
2180 (IMUL16rri GR16:$src1, imm:$src2)>;
2181 def : Pat<(mul GR32:$src1, imm:$src2),
2182 (IMUL32rri GR32:$src1, imm:$src2)>;
2183 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
2184 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
2187 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
2188 (IMUL16rmi addr:$src1, imm:$src2)>;
2189 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
2190 (IMUL32rmi addr:$src1, imm:$src2)>;
2191 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
2192 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;