Lines Matching +full:0 +full:x0000000080000000
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
29 let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP],
31 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs),
43 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
49 (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>;
58 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs),
61 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
67 (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>;
73 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
85 def VAARG_64 : I<0, Pseudo,
92 def VAARG_X32 : I<0, Pseudo,
107 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
114 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
124 def PROBED_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
131 def PROBED_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
139 def STACKALLOC_W_PROBING : I<0, Pseudo, (outs), (ins i64imm:$stacksize),
152 def DYN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size),
158 def DYN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size),
168 def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
171 def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src),
182 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
190 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
198 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET",
203 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from),
210 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
214 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
219 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
223 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
231 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
240 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
242 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
244 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
246 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
248 def SEH_StackAlign : I<0, Pseudo, (outs), (ins i32imm:$align),
250 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
252 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
254 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
256 def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
288 def MORESTACK_RET: I<0, Pseudo, (outs), (ins), "", []>;
293 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins), "", []>;
304 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
305 [(set GR32:$dst, 0)]>, Sched<[WriteZero]>;
310 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
311 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
312 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>;
321 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
323 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
336 def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "",
339 def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "",
349 def MOV32ri64 : I<0, Pseudo, (outs GR64:$dst), (ins i64i32imm:$src), "",
359 hasSideEffects = 0 in {
363 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "", []>;
364 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "", []>;
372 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins),
376 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins),
380 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins),
384 def REP_MOVSQ_32 : RI<0xA5, RawFrm, (outs), (ins),
391 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins),
395 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins),
399 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins),
403 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins),
412 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins),
417 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins),
422 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins),
427 def REP_STOSQ_32 : RI<0xAB, RawFrm, (outs), (ins),
435 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins),
440 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins),
445 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins),
451 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins),
473 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
477 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
493 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
497 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
501 def TLS_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
505 def TLS_base_addrX32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
515 def TLS_desc32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
517 def TLS_desc64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
528 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
541 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
553 def CMOV#NAME : I<0, Pseudo,
690 def OR32mi8Locked : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$zero),
705 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
761 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
794 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">;
795 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">;
796 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">;
797 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">;
798 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">;
803 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
807 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
811 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
816 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
820 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
824 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
831 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
835 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
859 def X86LBTest : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisPtrTy<1>,
868 def X86LBTestRM : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>,
882 def 16m : Ii8<0xBA, Form, (outs), (ins i16mem:$src1, i8imm:$src2),
886 def 32m : Ii8<0xBA, Form, (outs), (ins i32mem:$src1, i8imm:$src2),
890 def 64m : RIi8<0xBA, Form, (outs), (ins i64mem:$src1, i8imm:$src2),
920 defm LOCK_BTS_RM : ATOMIC_LOGIC_OP_RM<0xAB, "bts">;
921 defm LOCK_BTC_RM : ATOMIC_LOGIC_OP_RM<0xBB, "btc">;
922 defm LOCK_BTR_RM : ATOMIC_LOGIC_OP_RM<0xB3, "btr">;
950 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
957 isCodeGenOnly = 1, mayLoad = 1, mayStore = 1, hasSideEffects = 0 in {
958 def LCMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$ptr),
985 mayLoad = 1, mayStore = 1, hasSideEffects = 0,
988 I<0, Pseudo, (outs GR64:$dst),
997 mayLoad = 1, mayStore = 1, hasSideEffects = 0,
1000 I<0, Pseudo, (outs), (ins i128mem:$ptr, GR64:$rbx_input), "",
1011 I<0, Pseudo, (outs GR64:$dst),
1022 I<0, Pseudo, (outs), (ins GR32:$ecx, GR32:$eax, GR32:$ebx),
1028 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg", X86cas>;
1063 defm LXADD : ATOMIC_RMW_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add">, TB, LOCK;
1225 // Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves
1229 def : Pat<(simple_store (i16 0), addr:$dst), (AND16mi addr:$dst, 0)>;
1230 def : Pat<(simple_store (i32 0), addr:$dst), (AND32mi addr:$dst, 0)>;
1231 def : Pat<(simple_store (i64 0), addr:$dst), (AND64mi32 addr:$dst, 0)>;
1366 // TEST R,R is smaller than CMP R,0
1367 def : Pat<(X86cmp GR8:$src1, 0),
1369 def : Pat<(X86cmp GR16:$src1, 0),
1371 def : Pat<(X86cmp GR32:$src1, 0),
1373 def : Pat<(X86cmp GR64:$src1, 0),
1384 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1405 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1407 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1409 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1411 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1424 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1426 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1435 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1436 def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)),
1437 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1456 def ADD8rr_DB : I<0, Pseudo, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1459 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1462 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1465 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1470 def ADD8ri_DB : I<0, Pseudo,
1474 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1477 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1480 def ADD64ri32_DB : I<0, Pseudo,
1557 def : Pat<(add GR64:$src1, 0x0000000080000000),
1558 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1559 def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000),
1560 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1563 def : Pat<(add GR64:$src1, 0x0000000080000000),
1564 (SUB64ri32_ND GR64:$src1, 0xffffffff80000000)>;
1565 def : Pat<(X86add_flag_nocf GR64:$src1, 0x0000000080000000),
1566 (SUB64ri32_ND GR64:$src1, 0xffffffff80000000)>;
1568 def : Pat<(store (add (loadi64 addr:$dst), 0x0000000080000000), addr:$dst),
1569 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1571 def : Pat<(add(loadi64 addr:$src), 0x0000000080000000),
1572 (SUB64mi32_ND addr:$src, 0xffffffff80000000)>;
1604 (i64 0),
1613 (i64 0),
1627 def : Pat<(and GR32:$src1, 0xffff),
1630 def : Pat<(and GR32:$src1, 0xff),
1633 def : Pat<(and GR16:$src1, 0xff),
1638 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1639 (SUBREG_TO_REG (i64 0),
1643 def : Pat<(and GR64:$src, 0xffff),
1644 (SUBREG_TO_REG (i64 0),
1648 def : Pat<(and GR64:$src, 0xff),
1649 (SUBREG_TO_REG (i64 0),
1658 // Transformation function: Find the lowest 0.
1738 return Imm >= 0xff00 && Imm <= 0xffff;
1774 (i64 0),
1780 (i64 0),
1786 (i64 0),
1821 // where the least significant bit is not 0. However, the probability of this
2049 // sub 0, reg
2050 def : Pat<(X86sub_flag 0, GR8 :$src), (!cast<Instruction>(NEG8r#suffix) GR8 :$src)>;
2051 def : Pat<(X86sub_flag 0, GR16:$src), (!cast<Instruction>(NEG16r#suffix) GR16:$src)>;
2052 def : Pat<(X86sub_flag 0, GR32:$src), (!cast<Instruction>(NEG32r#suffix) GR32:$src)>;
2053 def : Pat<(X86sub_flag 0, GR64:$src), (!cast<Instruction>(NEG64r#suffix) GR64:$src)>;