Lines Matching refs:src1
19 (ins t.RegClass:$src1, t.RegClass:$src2, ccode:$cond),
21 [(set t.RegClass:$dst, (X86cmov t.RegClass:$src1,
25 (ins t.RegClass:$src1, t.MemOperand:$src2, ccode:$cond),
27 [(set t.RegClass:$dst, (X86cmov t.RegClass:$src1,
35 (ins t.RegClass:$src1, ccode:$cond),
38 (X86cmov 0, t.RegClass:$src1, timm:$cond, EFLAGS))]>, UseEFLAGS, NF;
40 (ins t.RegClass:$src1, ccode:$cond),
46 (ins t.RegClass:$src1, t.RegClass:$src2, ccode:$cond),
52 (ins t.MemOperand:$src1, ccode:$cond),
56 (ins t.RegClass:$src1, t.MemOperand:$src2, ccode:$cond),
62 (ins t.MemOperand:$dst, t.RegClass:$src1, ccode:$cond),
67 let Predicates = [HasCMOV, NoNDD], Constraints = "$dst = $src1" in {
93 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
94 (CMOV16rm GR16:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
95 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, timm:$cond, EFLAGS),
96 (CMOV32rm GR32:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
97 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, timm:$cond, EFLAGS),
98 (CMOV64rm GR64:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
102 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
103 (CMOV16rm_ND GR16:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
104 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, timm:$cond, EFLAGS),
105 (CMOV32rm_ND GR32:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
106 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, timm:$cond, EFLAGS),
107 (CMOV64rm_ND GR64:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
110 def : Pat<(X86cmov GR16:$src1, 0, timm:$cond, EFLAGS),
111 (CFCMOV16rr GR16:$src1, (inv_cond_XFORM timm:$cond))>;
112 def : Pat<(X86cmov GR32:$src1, 0, timm:$cond, EFLAGS),
113 (CFCMOV32rr GR32:$src1, (inv_cond_XFORM timm:$cond))>;
114 def : Pat<(X86cmov GR64:$src1, 0, timm:$cond, EFLAGS),
115 (CFCMOV64rr GR64:$src1, (inv_cond_XFORM timm:$cond))>;
117 def : Pat<(X86cload addr:$src1, 0, timm:$cond, EFLAGS),
118 (CFCMOV16rm addr:$src1, timm:$cond)>;
119 def : Pat<(X86cload addr:$src1, 0, timm:$cond, EFLAGS),
120 (CFCMOV32rm addr:$src1, timm:$cond)>;
121 def : Pat<(X86cload addr:$src1, 0, timm:$cond, EFLAGS),
122 (CFCMOV64rm addr:$src1, timm:$cond)>;
124 def : Pat<(X86cload addr:$src2, GR16:$src1, timm:$cond, EFLAGS),
125 (CFCMOV16rm_ND GR16:$src1, addr:$src2, timm:$cond)>;
126 def : Pat<(X86cload addr:$src2, GR32:$src1, timm:$cond, EFLAGS),
127 (CFCMOV32rm_ND GR32:$src1, addr:$src2, timm:$cond)>;
128 def : Pat<(X86cload addr:$src2, GR64:$src1, timm:$cond, EFLAGS),
129 (CFCMOV64rm_ND GR64:$src1, addr:$src2, timm:$cond)>;
131 def : Pat<(X86cstore GR16:$src2, addr:$src1, timm:$cond, EFLAGS),
132 (CFCMOV16mr addr:$src1, GR16:$src2, timm:$cond)>;
133 def : Pat<(X86cstore GR32:$src2, addr:$src1, timm:$cond, EFLAGS),
134 (CFCMOV32mr addr:$src1, GR32:$src2, timm:$cond)>;
135 def : Pat<(X86cstore GR64:$src2, addr:$src1, timm:$cond, EFLAGS),
136 (CFCMOV64mr addr:$src1, GR64:$src2, timm:$cond)>;