Lines Matching +full:pd +full:- +full:node
1 //===-- X86InstrArithmetic.td - Integer Arithmetic Instrs --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // LEA - Load Effective Address
47 //===----------------------------------------------------------------------===//
67 multiclass Mul<bits<8> o, string m, Format RegMRM, Format MemMRM, SDPatternOperator node> {
71 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
76 [(set AL, (node AL, GR8:$src1)), (implicit EFLAGS)]>;
85 [(set AL, (node AL, (loadi8 addr:$src1))), (implicit EFLAGS)]>;
97 def 16r_NF : MulDivOpR<o, RegMRM, m, Xi16, WriteIMul16, []>, NF, PD;
105 def 16m_NF : MulDivOpM<o, MemMRM, m, Xi16, WriteIMul16, []>, NF, PD;
114 def 16r_EVEX : MulDivOpR<o, RegMRM, m, Xi16, WriteIMul16, []>, PL, PD;
122 def 16m_EVEX : MulDivOpM<o, MemMRM, m, Xi16, WriteIMul16, []>, PL, PD;
159 def 16r_NF : MulDivOpR<o, RegMRM, m, Xi16, sched16, []>, NF, PD;
167 def 16m_NF : MulDivOpM<o, MemMRM, m, Xi16, sched16, []>, NF, PD;
176 def 16r_EVEX : MulDivOpR<o, RegMRM, m, Xi16, sched16, []>, PL, PD;
184 def 16m_EVEX : MulDivOpM<o, MemMRM, m, Xi16, sched16, []>, PL, PD;
201 // X = IMUL Y, Z --> X = IMUL Z, Y
208 // X = IMUL Y, Z --> X = IMUL Z, Y
231 def IMUL16rr_ND : IMulOpRR_RF<Xi16, WriteIMul16Reg, 1>, PD;
234 def IMUL16rm_ND : IMulOpRM_RF<Xi16, WriteIMul16Reg, 1>, PD;
240 def IMUL16rr_NF : IMulOpRR_R<Xi16, WriteIMul16Reg>, NF, PD;
243 def IMUL16rm_NF : IMulOpRM_R<Xi16, WriteIMul16Reg>, NF, PD;
247 def IMUL16rr_NF_ND : IMulOpRR_R<Xi16, WriteIMul16Reg, 1>, EVEX_NF, PD;
250 def IMUL16rm_NF_ND : IMulOpRM_R<Xi16, WriteIMul16Reg, 1>, EVEX_NF, PD;
254 def IMUL16rr_EVEX : IMulOpRR_RF<Xi16, WriteIMul16Reg>, PL, PD;
257 def IMUL16rm_EVEX : IMulOpRM_RF<Xi16, WriteIMul16Reg>, PL, PD;
311 def IMUL16rri8_NF : IMulOpRI8_R<Xi16, WriteIMul16Imm>, NF, PD;
314 def IMUL16rri_NF : IMulOpRI_R<Xi16, WriteIMul16Imm>, NF, PD;
317 def IMUL16rmi8_NF : IMulOpMI8_R<Xi16, WriteIMul16Imm>, NF, PD;
320 def IMUL16rmi_NF : IMulOpMI_R<Xi16, WriteIMul16Imm>, NF, PD;
324 def IMUL16rri8_EVEX : IMulOpRI8_R<Xi16, WriteIMul16Imm>, DefEFLAGS, PL, PD;
327 def IMUL16rri_EVEX : IMulOpRI_RF<Xi16, WriteIMul16Imm>, PL, PD;
330 def IMUL16rmi8_EVEX : IMulOpMI8_R<Xi16, WriteIMul16Imm>, DefEFLAGS, PL, PD;
333 def IMUL16rmi_EVEX : IMulOpMI_RF<Xi16, WriteIMul16Imm>, PL, PD;
361 def IMULZU16rri8 : IMulZUOpRI8_R<Xi16, WriteIMul16Imm>, ZU, PD;
362 def IMULZU16rmi8 : IMulZUOpMI8_R<Xi16, WriteIMul16Imm>, ZU, PD;
363 def IMULZU16rri : IMulZUOpRI_R<Xi16, WriteIMul16Imm>, ZU, PD;
364 def IMULZU16rmi : IMulZUOpMI_R<Xi16, WriteIMul16Imm>, ZU, PD;
375 //===----------------------------------------------------------------------===//
393 let Pattern = [(store (add (t.LoadNode addr:$src1), -1), addr:$src1),
400 let Pattern = [(set t.RegClass:$dst, EFLAGS, (add (t.LoadNode addr:$src1), -1))];
407 // IncDec_Alt - Instructions like "inc reg" short forms.
408 // Short forms only valid in 32-bit mode. Selected during MCInst lowering.
429 def INC16r_ND : IncOpR_RF<Xi16, 1>, PD;
433 def DEC16r_ND : DecOpR_RF<Xi16, 1>, PD;
439 def INC16r_NF : IncOpR_R<Xi16>, NF, PD;
443 def DEC16r_NF : DecOpR_R<Xi16>, NF, PD;
447 def INC16r_NF_ND : IncOpR_R<Xi16, 1>, NF, PD;
451 def DEC16r_NF_ND : DecOpR_R<Xi16, 1>, NF, PD;
455 def INC16r_EVEX : IncOpR_RF<Xi16>, PL, PD;
459 def DEC16r_EVEX : DecOpR_RF<Xi16>, PL, PD;
478 def INC16m_ND : IncOpM_RF<Xi16>, PD;
481 def DEC16m_ND : DecOpM_RF<Xi16>, PD;
488 def INC16m_NF : IncOpM_M<Xi16>, NF, PD;
492 def DEC16m_NF : DecOpM_M<Xi16>, NF, PD;
496 def INC16m_NF_ND : IncOpM_R<Xi16>, NF, PD;
500 def DEC16m_NF_ND : DecOpM_R<Xi16>, NF, PD;
504 def INC16m_EVEX : IncOpM_MF<Xi16>, PL, PD;
508 def DEC16m_EVEX : DecOpM_MF<Xi16>, PL, PD;
513 //===----------------------------------------------------------------------===//
543 def NEG16r_ND : NegOpR_RF<Xi16, 1>, PD;
548 def NOT16r_ND : NotOpR_R<Xi16, 1>, PD;
553 def NEG16r_NF_ND : NegOpR_R<Xi16, 1>, EVEX_NF, PD;
565 def NEG16m_ND : NegOpM_RF<Xi16>, PD;
570 def NEG16m_NF_ND : NegOpM_R<Xi16>, EVEX_NF, PD;
582 def NOT16m_ND : NotOpM_R<Xi16>, PD;
589 def NEG16r_NF : NegOpR_R<Xi16>, NF, PD;
593 def NEG16m_NF : NegOpM_M<Xi16>, NF, PD;
598 def NEG16r_EVEX : NegOpR_RF<Xi16>, PL, PD;
603 def NOT16r_EVEX : NotOpR_R<Xi16>, PL, PD;
608 def NEG16m_EVEX : NegOpM_MF<Xi16>, PL, PD;
613 def NOT16m_EVEX : NotOpM_M<Xi16>, PL, PD;
618 /// ArithBinOp_RF - This is an arithmetic binary operator where the pattern is
638 def 16rr_ND : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag, 1>, PD;
642 def 16rr_NF_ND : BinOpRR_R<BaseOpc, mnemonic, Xi16, 1>, EVEX_NF, PD;
648 def 16rr_NF : BinOpRR_R<BaseOpc, mnemonic, Xi16>, NF, PD;
652 def 16rr_EVEX : BinOpRR_RF<BaseOpc, mnemonic, Xi16, null_frag>, PL, PD;
664 def 16rr_EVEX_REV : BinOpRR_RF_Rev<BaseOpc2, mnemonic, Xi16>, PL, PD;
668 def 16rr_ND_REV : BinOpRR_RF_Rev<BaseOpc2, mnemonic, Xi16, 1>, PD;
672 def 16rr_NF_REV : BinOpRR_R_Rev<BaseOpc2, mnemonic, Xi16>, NF, PD;
676 def 16rr_NF_ND_REV : BinOpRR_R_Rev<BaseOpc2, mnemonic, Xi16, 1>, EVEX_NF, PD;
689 def 16rm_ND : BinOpRM_RF<BaseOpc2, mnemonic, Xi16, opnodeflag, 1>, PD;
693 def 16rm_NF_ND : BinOpRM_R<BaseOpc2, mnemonic, Xi16, 1>, EVEX_NF, PD;
699 def 16rm_NF : BinOpRM_R<BaseOpc2, mnemonic, Xi16>, NF, PD;
703 def 16rm_EVEX : BinOpRM_RF<BaseOpc2, mnemonic, Xi16, null_frag>, PL, PD;
721 def 16ri8_ND : BinOpRI8_RF<0x83, mnemonic, Xi16, RegMRM, 1>, PD;
725 def 16ri_ND : BinOpRI_RF<0x81, mnemonic, Xi16, opnodeflag, RegMRM, 1>, PD;
728 def 16ri8_NF_ND : BinOpRI8_R<0x83, mnemonic, Xi16, RegMRM, 1>, EVEX_NF, PD;
732 def 16ri_NF_ND : BinOpRI_R<0x81, mnemonic, Xi16, RegMRM, 1>, EVEX_NF, PD;
737 def 16ri8_NF : BinOpRI8_R<0x83, mnemonic, Xi16, RegMRM>, NF, PD;
741 def 16ri_NF : BinOpRI_R<0x81, mnemonic, Xi16, RegMRM>, NF, PD;
744 def 16ri8_EVEX : BinOpRI8_RF<0x83, mnemonic, Xi16, RegMRM>, PL, PD;
748 def 16ri_EVEX : BinOpRI_RF<0x81, mnemonic, Xi16, null_frag, RegMRM>, PL, PD;
759 defvar node = !if(!eq(CommutableRR, 0), opnode, null_frag);
760 def 8mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi8 , node>;
761 def 16mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi16, node>, PD;
762 def 32mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi32, node>;
763 def 64mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi64, node>;
765 def 16mr_NF_ND : BinOpMR_R<BaseOpc, mnemonic, Xi16>, EVEX_NF, PD;
771 def 16mr_NF : BinOpMR_M<BaseOpc, mnemonic, Xi16>, NF, PD;
775 def 16mr_EVEX : BinOpMR_MF<BaseOpc, mnemonic, Xi16, null_frag>, PL, PD;
792 def 16mi8_ND : BinOpMI8_RF<mnemonic, Xi16, MemMRM>, PD;
796 def 16mi_ND : BinOpMI_RF<0x81, mnemonic, Xi16, opnode, MemMRM>, PD;
799 def 16mi8_NF_ND : BinOpMI8_R<mnemonic, Xi16, MemMRM>, NF, PD;
803 def 16mi_NF_ND : BinOpMI_R<0x81, mnemonic, Xi16, MemMRM>, NF, PD;
808 def 16mi8_NF : BinOpMI8_M<mnemonic, Xi16, MemMRM>, NF, PD;
812 def 16mi_NF : BinOpMI_M<0x81, mnemonic, Xi16, MemMRM>, NF, PD;
815 def 16mi8_EVEX : BinOpMI8_MF<mnemonic, Xi16, MemMRM>, PL, PD;
819 def 16mi_EVEX : BinOpMI_MF<0x81, mnemonic, Xi16, null_frag, MemMRM>, PL, PD;
825 // not in 64-bit mode.
837 /// ArithBinOp_RFF - This is an arithmetic binary operator where the pattern is
838 /// defined with "(set GPR:$dst, EFLAGS, (node LHS, RHS, EFLAGS))" like ADC and
859 def 16rr_ND : BinOpRRF_RF<BaseOpc, mnemonic, Xi16, opnode, 1>, PD;
868 def 16rr_EVEX : BinOpRRF_RF<BaseOpc, mnemonic, Xi16, null_frag>, PL, PD;
879 def 16rr_ND_REV : BinOpRRF_RF_Rev<BaseOpc2, mnemonic, Xi16, 1>, PD;
883 def 16rr_EVEX_REV : BinOpRRF_RF_Rev<BaseOpc2, mnemonic, Xi16>, PL, PD;
896 def 16rm_ND : BinOpRMF_RF<BaseOpc2, mnemonic, Xi16, opnode, 1>, PD;
902 def 16rm_EVEX : BinOpRMF_RF<BaseOpc2, mnemonic, Xi16, opnode>, PL, PD;
925 def 16ri8_ND : BinOpRI8F_RF<0x83, mnemonic, Xi16, RegMRM, 1>, PD;
928 def 16ri_ND : BinOpRIF_RF<0x81, mnemonic, Xi16, opnode, RegMRM, 1>, PD;
935 def 16ri8_EVEX : BinOpRI8F_RF<0x83, mnemonic, Xi16, RegMRM>, PL, PD;
938 def 16ri_EVEX : BinOpRIF_RF<0x81, mnemonic, Xi16, opnode, RegMRM>, PL, PD;
948 defvar node = !if(!eq(CommutableRR, 0), opnode, null_frag);
949 def 8mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi8 , node>;
950 def 16mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi16, node>, PD;
951 def 32mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi32, node>;
952 def 64mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi64, node>;
956 def 16mr_EVEX : BinOpMRF_MF<BaseOpc, mnemonic, Xi16, null_frag>, PL, PD;
975 def 16mi8_ND : BinOpMI8F_RF<mnemonic, Xi16, MemMRM>, PD;
978 def 16mi_ND : BinOpMIF_RF<0x81, mnemonic, Xi16, opnode, MemMRM>, PD;
984 def 16mi8_EVEX : BinOpMI8F_MF<mnemonic, Xi16, MemMRM>, PL, PD;
987 def 16mi_EVEX : BinOpMIF_MF<0x81, mnemonic, Xi16, opnode, MemMRM>, PL, PD;
993 // not in 64-bit mode.
1005 /// ArithBinOp_F - This is an arithmetic binary operator where the pattern is
1065 // not in 64-bit mode.
1093 // __builtin_parity where the last step xors an h-register with an l-register.
1294 //===----------------------------------------------------------------------===//
1352 //===----------------------------------------------------------------------===//
1355 multiclass AndN<X86TypeInfo t, SDPatternOperator node, string suffix = ""> {
1357 [(set t.RegClass:$dst, EFLAGS, (node (not t.RegClass:$src1),
1360 [(set t.RegClass:$dst, EFLAGS, (node (not t.RegClass:$src1),
1372 let AddedComplexity = -6 in {
1392 let Predicates = [HasBMI, NoEGPR], AddedComplexity = -6 in
1395 let Predicates = [HasBMI, HasEGPR], AddedComplexity = -6 in
1398 //===----------------------------------------------------------------------===//
1444 //===----------------------------------------------------------------------===//
1450 def ADCX32rr : BinOpRRF_RF<0xF6, "adcx", Xi32>, T8, PD;
1451 def ADCX64rr : BinOpRRF_RF<0xF6, "adcx", Xi64>, T8, PD;
1455 def ADCX32rr_EVEX : BinOpRRF_RF<0x66, "adcx", Xi32>, EVEX, T_MAP4, PD;
1456 def ADCX64rr_EVEX : BinOpRRF_RF<0x66, "adcx", Xi64>, EVEX, T_MAP4, PD;
1459 def ADCX32rr_ND : BinOpRRF_RF<0x66, "adcx", Xi32, null_frag, 1>, PD;
1460 def ADCX64rr_ND : BinOpRRF_RF<0x66, "adcx", Xi64, null_frag, 1>, PD;
1466 def ADCX32rm : BinOpRMF_RF<0xF6, "adcx", Xi32>, T8, PD;
1467 def ADCX64rm : BinOpRMF_RF<0xF6, "adcx", Xi64>, T8, PD;
1471 def ADCX32rm_EVEX : BinOpRMF_RF<0x66, "adcx", Xi32>, EVEX, T_MAP4, PD;
1472 def ADCX64rm_EVEX : BinOpRMF_RF<0x66, "adcx", Xi64>, EVEX, T_MAP4, PD;
1475 def ADCX32rm_ND : BinOpRMF_RF<0x66, "adcx", Xi32, null_frag, 1>, PD;
1476 def ADCX64rm_ND : BinOpRMF_RF<0x66, "adcx", Xi64, null_frag, 1>, PD;