Lines Matching +full:64 +full:m
50 class MulDivOpR<bits<8> o, Format f, string m, X86TypeInfo t,
52 : UnaryOpR<o, f, m, "$src1", t, (outs), p> {
56 class MulDivOpM<bits<8> o, Format f, string m, X86TypeInfo t,
58 : UnaryOpM<o, f, m, "$src1", t, (outs), p> {
67 multiclass Mul<bits<8> o, string m, Format RegMRM, Format MemMRM, SDPatternOperator node> {
75 def 8r : MulDivOpR<o, RegMRM, m, Xi8, WriteIMul8,
78 def 16r : MulDivOpR<o, RegMRM, m, Xi16, WriteIMul16, []>, OpSize16;
80 def 32r : MulDivOpR<o, RegMRM, m, Xi32, WriteIMul32, []>, OpSize32;
82 def 64r : MulDivOpR<o, RegMRM, m, Xi64, WriteIMul64, []>;
84 def 8m : MulDivOpM<o, MemMRM, m, Xi8, WriteIMul8,
87 def 16m : MulDivOpM<o, MemMRM, m, Xi16, WriteIMul16, []>, OpSize16;
89 def 32m : MulDivOpM<o, MemMRM, m, Xi32, WriteIMul32, []>, OpSize32;
91 def 64m : MulDivOpM<o, MemMRM, m, Xi64, WriteIMul64, []>, Requires<[In64BitMode]>;
95 def 8r_NF : MulDivOpR<o, RegMRM, m, Xi8, WriteIMul8, []>, NF;
97 def 16r_NF : MulDivOpR<o, RegMRM, m, Xi16, WriteIMul16, []>, NF, PD;
99 def 32r_NF : MulDivOpR<o, RegMRM, m, Xi32, WriteIMul32, []>, NF;
101 def 64r_NF : MulDivOpR<o, RegMRM, m, Xi64, WriteIMul64, []>, NF;
103 def 8m_NF : MulDivOpM<o, MemMRM, m, Xi8, WriteIMul8, []>, NF;
105 def 16m_NF : MulDivOpM<o, MemMRM, m, Xi16, WriteIMul16, []>, NF, PD;
107 def 32m_NF : MulDivOpM<o, MemMRM, m, Xi32, WriteIMul32, []>, NF;
109 def 64m_NF : MulDivOpM<o, MemMRM, m, Xi64, WriteIMul64, []>, NF;
112 def 8r_EVEX : MulDivOpR<o, RegMRM, m, Xi8, WriteIMul8, []>, PL;
114 def 16r_EVEX : MulDivOpR<o, RegMRM, m, Xi16, WriteIMul16, []>, PL, PD;
116 def 32r_EVEX : MulDivOpR<o, RegMRM, m, Xi32, WriteIMul32, []>, PL;
118 def 64r_EVEX : MulDivOpR<o, RegMRM, m, Xi64, WriteIMul64, []>, PL;
120 def 8m_EVEX : MulDivOpM<o, MemMRM, m, Xi8, WriteIMul8, []>, PL;
122 def 16m_EVEX : MulDivOpM<o, MemMRM, m, Xi16, WriteIMul16, []>, PL, PD;
124 def 32m_EVEX : MulDivOpM<o, MemMRM, m, Xi32, WriteIMul32, []>, PL;
126 def 64m_EVEX : MulDivOpM<o, MemMRM, m, Xi64, WriteIMul64, []>, PL;
133 multiclass Div<bits<8> o, string m, Format RegMRM, Format MemMRM> {
134 defvar sched8 = !if(!eq(m, "div"), WriteDiv8, WriteIDiv8);
135 defvar sched16 = !if(!eq(m, "div"), WriteDiv16, WriteIDiv16);
136 defvar sched32 = !if(!eq(m, "div"), WriteDiv32, WriteIDiv32);
137 defvar sched64 = !if(!eq(m, "div"), WriteDiv64, WriteIDiv64);
139 def 8r : MulDivOpR<o, RegMRM, m, Xi8, sched8, []>;
141 def 16r : MulDivOpR<o, RegMRM, m, Xi16, sched16, []>, OpSize16;
143 def 32r : MulDivOpR<o, RegMRM, m, Xi32, sched32, []>, OpSize32;
145 def 64r : MulDivOpR<o, RegMRM, m, Xi64, sched64, []>;
147 def 8m : MulDivOpM<o, MemMRM, m, Xi8, sched8, []>;
149 def 16m : MulDivOpM<o, MemMRM, m, Xi16, sched16, []>, OpSize16;
151 def 32m : MulDivOpM<o, MemMRM, m, Xi32, sched32, []>, OpSize32;
153 def 64m : MulDivOpM<o, MemMRM, m, Xi64, sched64, []>, Requires<[In64BitMode]>;
157 def 8r_NF : MulDivOpR<o, RegMRM, m, Xi8, sched8, []>, NF;
159 def 16r_NF : MulDivOpR<o, RegMRM, m, Xi16, sched16, []>, NF, PD;
161 def 32r_NF : MulDivOpR<o, RegMRM, m, Xi32, sched32, []>, NF;
163 def 64r_NF : MulDivOpR<o, RegMRM, m, Xi64, sched64, []>, NF;
165 def 8m_NF : MulDivOpM<o, MemMRM, m, Xi8, sched8, []>, NF;
167 def 16m_NF : MulDivOpM<o, MemMRM, m, Xi16, sched16, []>, NF, PD;
169 def 32m_NF : MulDivOpM<o, MemMRM, m, Xi32, sched32, []>, NF;
171 def 64m_NF : MulDivOpM<o, MemMRM, m, Xi64, sched64, []>, NF;
174 def 8r_EVEX : MulDivOpR<o, RegMRM, m, Xi8, sched8, []>, PL;
176 def 16r_EVEX : MulDivOpR<o, RegMRM, m, Xi16, sched16, []>, PL, PD;
178 def 32r_EVEX : MulDivOpR<o, RegMRM, m, Xi32, sched32, []>, PL;
180 def 64r_EVEX : MulDivOpR<o, RegMRM, m, Xi64, sched64, []>, PL;
182 def 8m_EVEX : MulDivOpM<o, MemMRM, m, Xi8, sched8, []>, PL;
184 def 16m_EVEX : MulDivOpM<o, MemMRM, m, Xi16, sched16, []>, PL, PD;
186 def 32m_EVEX : MulDivOpM<o, MemMRM, m, Xi32, sched32, []>, PL;
188 def 64m_EVEX : MulDivOpM<o, MemMRM, m, Xi64, sched64, []>, PL;
409 class IncDec_Alt<bits<8> o, string m, X86TypeInfo t>
410 : UnaryOpR_RF<o, AddRegFrm, m, t, null_frag>, Requires<[Not64BitMode]>;
634 def 64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
640 def 64rr_ND : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag, 1>;
644 def 64rr_NF_ND : BinOpRR_R<BaseOpc, mnemonic, Xi64, 1>, EVEX_NF;
650 def 64rr_NF : BinOpRR_R<BaseOpc, mnemonic, Xi64>, NF;
654 def 64rr_EVEX : BinOpRR_RF<BaseOpc, mnemonic, Xi64, null_frag>, PL;
661 def 64rr_REV : BinOpRR_RF_Rev<BaseOpc2, mnemonic, Xi64>;
666 def 64rr_EVEX_REV : BinOpRR_RF_Rev<BaseOpc2, mnemonic, Xi64>, PL;
670 def 64rr_ND_REV : BinOpRR_RF_Rev<BaseOpc2, mnemonic, Xi64, 1>;
674 def 64rr_NF_REV : BinOpRR_R_Rev<BaseOpc2, mnemonic, Xi64>, NF;
678 def 64rr_NF_ND_REV : BinOpRR_R_Rev<BaseOpc2, mnemonic, Xi64, 1>, EVEX_NF;
685 def 64rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi64, opnodeflag>;
691 def 64rm_ND : BinOpRM_RF<BaseOpc2, mnemonic, Xi64, opnodeflag, 1>;
695 def 64rm_NF_ND : BinOpRM_R<BaseOpc2, mnemonic, Xi64, 1>, EVEX_NF;
701 def 64rm_NF : BinOpRM_R<BaseOpc2, mnemonic, Xi64>, NF;
705 def 64rm_EVEX : BinOpRM_RF<BaseOpc2, mnemonic, Xi64, null_frag>, PL;
714 def 64ri8 : BinOpRI8_RF<0x83, mnemonic, Xi64, RegMRM>;
718 def 64ri32: BinOpRI_RF<0x81, mnemonic, Xi64, opnodeflag, RegMRM>;
723 def 64ri8_ND : BinOpRI8_RF<0x83, mnemonic, Xi64, RegMRM, 1>;
727 def 64ri32_ND: BinOpRI_RF<0x81, mnemonic, Xi64, opnodeflag, RegMRM, 1>;
730 def 64ri8_NF_ND : BinOpRI8_R<0x83, mnemonic, Xi64, RegMRM, 1>, EVEX_NF;
734 def 64ri32_NF_ND : BinOpRI_R<0x81, mnemonic, Xi64, RegMRM, 1>, EVEX_NF;
739 def 64ri8_NF : BinOpRI8_R<0x83, mnemonic, Xi64, RegMRM>, NF;
743 def 64ri32_NF : BinOpRI_R<0x81, mnemonic, Xi64, RegMRM>, NF;
746 def 64ri8_EVEX : BinOpRI8_RF<0x83, mnemonic, Xi64, RegMRM>, PL;
750 def 64ri32_EVEX: BinOpRI_RF<0x81, mnemonic, Xi64, null_frag, RegMRM>, PL;
757 def 64mr : BinOpMR_MF<BaseOpc, mnemonic, Xi64, opnode>;
763 def 64mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi64, node>;
767 def 64mr_NF_ND : BinOpMR_R<BaseOpc, mnemonic, Xi64>, EVEX_NF;
773 def 64mr_NF : BinOpMR_M<BaseOpc, mnemonic, Xi64>, NF;
777 def 64mr_EVEX : BinOpMR_MF<BaseOpc, mnemonic, Xi64, null_frag>, PL;
785 def 64mi8 : BinOpMI8_MF<mnemonic, Xi64, MemMRM>;
790 def 64mi32 : BinOpMI_MF<0x81, mnemonic, Xi64, opnode, MemMRM>;
794 def 64mi8_ND : BinOpMI8_RF<mnemonic, Xi64, MemMRM>;
798 def 64mi32_ND : BinOpMI_RF<0x81, mnemonic, Xi64, opnode, MemMRM>;
801 def 64mi8_NF_ND : BinOpMI8_R<mnemonic, Xi64, MemMRM>, NF;
805 def 64mi32_NF_ND : BinOpMI_R<0x81, mnemonic, Xi64, MemMRM>, NF;
810 def 64mi8_NF : BinOpMI8_M<mnemonic, Xi64, MemMRM>, NF;
814 def 64mi32_NF : BinOpMI_M<0x81, mnemonic, Xi64, MemMRM>, NF;
817 def 64mi8_EVEX : BinOpMI8_MF<mnemonic, Xi64, MemMRM>, PL;
821 def 64mi32_EVEX : BinOpMI_MF<0x81, mnemonic, Xi64, null_frag, MemMRM>, PL;
825 // not in 64-bit mode.
834 def 64i32 : BinOpAI_AF<BaseOpc4, mnemonic, Xi64, RAX, "{$src, %rax|rax, $src}">;
853 def 64rr : BinOpRRF_RF<BaseOpc, mnemonic, Xi64, opnode>;
861 def 64rr_ND : BinOpRRF_RF<BaseOpc, mnemonic, Xi64, opnode, 1>;
870 def 64rr_EVEX : BinOpRRF_RF<BaseOpc, mnemonic, Xi64, null_frag>, PL;
876 def 64rr_REV : BinOpRRF_RF_Rev<BaseOpc2, mnemonic, Xi64>;
881 def 64rr_ND_REV : BinOpRRF_RF_Rev<BaseOpc2, mnemonic, Xi64, 1>;
885 def 64rr_EVEX_REV : BinOpRRF_RF_Rev<BaseOpc2, mnemonic, Xi64>, PL;
892 def 64rm : BinOpRMF_RF<BaseOpc2, mnemonic, Xi64, opnode>;
898 def 64rm_ND : BinOpRMF_RF<BaseOpc2, mnemonic, Xi64, opnode, 1>;
904 def 64rm_EVEX : BinOpRMF_RF<BaseOpc2, mnemonic, Xi64, opnode>, PL;
914 def 64ri8 : BinOpRI8F_RF<0x83, mnemonic, Xi64, RegMRM>;
918 def 64ri32: BinOpRIF_RF<0x81, mnemonic, Xi64, opnode, RegMRM>;
927 def 64ri8_ND : BinOpRI8F_RF<0x83, mnemonic, Xi64, RegMRM, 1>;
930 def 64ri32_ND: BinOpRIF_RF<0x81, mnemonic, Xi64, opnode, RegMRM, 1>;
937 def 64ri8_EVEX : BinOpRI8F_RF<0x83, mnemonic, Xi64, RegMRM>, PL;
940 def 64ri32_EVEX: BinOpRIF_RF<0x81, mnemonic, Xi64, opnode, RegMRM>, PL;
946 def 64mr : BinOpMRF_MF<BaseOpc, mnemonic, Xi64, opnode>;
952 def 64mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi64, node>;
958 def 64mr_EVEX : BinOpMRF_MF<BaseOpc, mnemonic, Xi64, null_frag>, PL;
967 def 64mi8 : BinOpMI8F_MF<mnemonic, Xi64, MemMRM>;
971 def 64mi32 : BinOpMIF_MF<0x81, mnemonic, Xi64, opnode, MemMRM>;
977 def 64mi8_ND : BinOpMI8F_RF<mnemonic, Xi64, MemMRM>;
980 def 64mi32_ND : BinOpMIF_RF<0x81, mnemonic, Xi64, opnode, MemMRM>;
986 def 64mi8_EVEX : BinOpMI8F_MF<mnemonic, Xi64, MemMRM>, PL;
989 def 64mi32_EVEX : BinOpMIF_MF<0x81, mnemonic, Xi64, opnode, MemMRM>, PL;
993 // not in 64-bit mode.
1002 def 64i32 : BinOpAIF_AF<BaseOpc4, mnemonic, Xi64, RAX, "{$src, %rax|rax, $src}">;
1018 def 64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;
1025 def 64rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi64>;
1030 def 64rm : BinOpRM_F<BaseOpc2, mnemonic, Xi64, opnode>;
1039 def 64ri8 : BinOpRI8_F<0x83, mnemonic, Xi64, RegMRM>;
1043 def 64ri32: BinOpRI_F<0x81, mnemonic, Xi64, opnode, RegMRM>;
1049 def 64mr : BinOpMR_F<BaseOpc, mnemonic, Xi64, opnode>;
1056 def 64mi8 : BinOpMI8_F<mnemonic, Xi64, MemMRM>;
1062 def 64mi32 : BinOpMI_F<0x81, mnemonic, Xi64, opnode, MemMRM>;
1065 // not in 64-bit mode.
1075 def 64i32 : BinOpAI_F<BaseOpc4, mnemonic, Xi64, RAX, "{$src, %rax|rax, $src}">;
1158 (!cast<Instruction>(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>;
1167 (!cast<Instruction>(NAME#"64mi32") addr:$dst, i64relocImmSExt32_su:$src)>;
1177 (!cast<Instruction>(NAME#"64ri32_ND") GR64:$src1, i64relocImmSExt32_su:$src2)>;
1186 (!cast<Instruction>(NAME#"64mi32_ND") addr:$dst, i64relocImmSExt32_su:$src)>;
1199 (!cast<Instruction>(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>;
1208 (!cast<Instruction>(NAME#"64mi32") addr:$dst, i64relocImmSExt32_su:$src)>;
1218 (!cast<Instruction>(NAME#"64ri32_ND") GR64:$src1, i64relocImmSExt32_su:$src2)>;
1227 (!cast<Instruction>(NAME#"64mi32_ND") addr:$dst, i64relocImmSExt32_su:$src)>;
1239 (!cast<Instruction>(NAME#"64ri32") GR64:$src1, i64relocImmSExt32_su:$src2)>;
1248 (!cast<Instruction>(NAME#"64mi32") addr:$src1, i64relocImmSExt32_su:$src2)>;