Lines Matching +full:32 +full:m
50 class MulDivOpR<bits<8> o, Format f, string m, X86TypeInfo t,
52 : UnaryOpR<o, f, m, "$src1", t, (outs), p> {
56 class MulDivOpM<bits<8> o, Format f, string m, X86TypeInfo t,
58 : UnaryOpM<o, f, m, "$src1", t, (outs), p> {
67 multiclass Mul<bits<8> o, string m, Format RegMRM, Format MemMRM, SDPatternOperator node> {
75 def 8r : MulDivOpR<o, RegMRM, m, Xi8, WriteIMul8,
78 def 16r : MulDivOpR<o, RegMRM, m, Xi16, WriteIMul16, []>, OpSize16;
80 def 32r : MulDivOpR<o, RegMRM, m, Xi32, WriteIMul32, []>, OpSize32;
82 def 64r : MulDivOpR<o, RegMRM, m, Xi64, WriteIMul64, []>;
84 def 8m : MulDivOpM<o, MemMRM, m, Xi8, WriteIMul8,
87 def 16m : MulDivOpM<o, MemMRM, m, Xi16, WriteIMul16, []>, OpSize16;
89 def 32m : MulDivOpM<o, MemMRM, m, Xi32, WriteIMul32, []>, OpSize32;
91 def 64m : MulDivOpM<o, MemMRM, m, Xi64, WriteIMul64, []>, Requires<[In64BitMode]>;
95 def 8r_NF : MulDivOpR<o, RegMRM, m, Xi8, WriteIMul8, []>, NF;
97 def 16r_NF : MulDivOpR<o, RegMRM, m, Xi16, WriteIMul16, []>, NF, PD;
99 def 32r_NF : MulDivOpR<o, RegMRM, m, Xi32, WriteIMul32, []>, NF;
101 def 64r_NF : MulDivOpR<o, RegMRM, m, Xi64, WriteIMul64, []>, NF;
103 def 8m_NF : MulDivOpM<o, MemMRM, m, Xi8, WriteIMul8, []>, NF;
105 def 16m_NF : MulDivOpM<o, MemMRM, m, Xi16, WriteIMul16, []>, NF, PD;
107 def 32m_NF : MulDivOpM<o, MemMRM, m, Xi32, WriteIMul32, []>, NF;
109 def 64m_NF : MulDivOpM<o, MemMRM, m, Xi64, WriteIMul64, []>, NF;
112 def 8r_EVEX : MulDivOpR<o, RegMRM, m, Xi8, WriteIMul8, []>, PL;
114 def 16r_EVEX : MulDivOpR<o, RegMRM, m, Xi16, WriteIMul16, []>, PL, PD;
116 def 32r_EVEX : MulDivOpR<o, RegMRM, m, Xi32, WriteIMul32, []>, PL;
118 def 64r_EVEX : MulDivOpR<o, RegMRM, m, Xi64, WriteIMul64, []>, PL;
120 def 8m_EVEX : MulDivOpM<o, MemMRM, m, Xi8, WriteIMul8, []>, PL;
122 def 16m_EVEX : MulDivOpM<o, MemMRM, m, Xi16, WriteIMul16, []>, PL, PD;
124 def 32m_EVEX : MulDivOpM<o, MemMRM, m, Xi32, WriteIMul32, []>, PL;
126 def 64m_EVEX : MulDivOpM<o, MemMRM, m, Xi64, WriteIMul64, []>, PL;
133 multiclass Div<bits<8> o, string m, Format RegMRM, Format MemMRM> {
134 defvar sched8 = !if(!eq(m, "div"), WriteDiv8, WriteIDiv8);
135 defvar sched16 = !if(!eq(m, "div"), WriteDiv16, WriteIDiv16);
136 defvar sched32 = !if(!eq(m, "div"), WriteDiv32, WriteIDiv32);
137 defvar sched64 = !if(!eq(m, "div"), WriteDiv64, WriteIDiv64);
139 def 8r : MulDivOpR<o, RegMRM, m, Xi8, sched8, []>;
141 def 16r : MulDivOpR<o, RegMRM, m, Xi16, sched16, []>, OpSize16;
143 def 32r : MulDivOpR<o, RegMRM, m, Xi32, sched32, []>, OpSize32;
145 def 64r : MulDivOpR<o, RegMRM, m, Xi64, sched64, []>;
147 def 8m : MulDivOpM<o, MemMRM, m, Xi8, sched8, []>;
149 def 16m : MulDivOpM<o, MemMRM, m, Xi16, sched16, []>, OpSize16;
151 def 32m : MulDivOpM<o, MemMRM, m, Xi32, sched32, []>, OpSize32;
153 def 64m : MulDivOpM<o, MemMRM, m, Xi64, sched64, []>, Requires<[In64BitMode]>;
157 def 8r_NF : MulDivOpR<o, RegMRM, m, Xi8, sched8, []>, NF;
159 def 16r_NF : MulDivOpR<o, RegMRM, m, Xi16, sched16, []>, NF, PD;
161 def 32r_NF : MulDivOpR<o, RegMRM, m, Xi32, sched32, []>, NF;
163 def 64r_NF : MulDivOpR<o, RegMRM, m, Xi64, sched64, []>, NF;
165 def 8m_NF : MulDivOpM<o, MemMRM, m, Xi8, sched8, []>, NF;
167 def 16m_NF : MulDivOpM<o, MemMRM, m, Xi16, sched16, []>, NF, PD;
169 def 32m_NF : MulDivOpM<o, MemMRM, m, Xi32, sched32, []>, NF;
171 def 64m_NF : MulDivOpM<o, MemMRM, m, Xi64, sched64, []>, NF;
174 def 8r_EVEX : MulDivOpR<o, RegMRM, m, Xi8, sched8, []>, PL;
176 def 16r_EVEX : MulDivOpR<o, RegMRM, m, Xi16, sched16, []>, PL, PD;
178 def 32r_EVEX : MulDivOpR<o, RegMRM, m, Xi32, sched32, []>, PL;
180 def 64r_EVEX : MulDivOpR<o, RegMRM, m, Xi64, sched64, []>, PL;
182 def 8m_EVEX : MulDivOpM<o, MemMRM, m, Xi8, sched8, []>, PL;
184 def 16m_EVEX : MulDivOpM<o, MemMRM, m, Xi16, sched16, []>, PL, PD;
186 def 32m_EVEX : MulDivOpM<o, MemMRM, m, Xi32, sched32, []>, PL;
188 def 64m_EVEX : MulDivOpM<o, MemMRM, m, Xi64, sched64, []>, PL;
408 // Short forms only valid in 32-bit mode. Selected during MCInst lowering.
409 class IncDec_Alt<bits<8> o, string m, X86TypeInfo t>
410 : UnaryOpR_RF<o, AddRegFrm, m, t, null_frag>, Requires<[Not64BitMode]>;
633 def 32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>, OpSize32;
639 def 32rr_ND : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag, 1>;
643 def 32rr_NF_ND : BinOpRR_R<BaseOpc, mnemonic, Xi32, 1>, EVEX_NF;
649 def 32rr_NF : BinOpRR_R<BaseOpc, mnemonic, Xi32>, NF;
653 def 32rr_EVEX : BinOpRR_RF<BaseOpc, mnemonic, Xi32, null_frag>, PL;
660 def 32rr_REV : BinOpRR_RF_Rev<BaseOpc2, mnemonic, Xi32>, OpSize32;
665 def 32rr_EVEX_REV : BinOpRR_RF_Rev<BaseOpc2, mnemonic, Xi32>, PL;
669 def 32rr_ND_REV : BinOpRR_RF_Rev<BaseOpc2, mnemonic, Xi32, 1>;
673 def 32rr_NF_REV : BinOpRR_R_Rev<BaseOpc2, mnemonic, Xi32>, NF;
677 def 32rr_NF_ND_REV : BinOpRR_R_Rev<BaseOpc2, mnemonic, Xi32, 1>, EVEX_NF;
684 def 32rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi32, opnodeflag>, OpSize32;
690 def 32rm_ND : BinOpRM_RF<BaseOpc2, mnemonic, Xi32, opnodeflag, 1>;
694 def 32rm_NF_ND : BinOpRM_R<BaseOpc2, mnemonic, Xi32, 1>, EVEX_NF;
700 def 32rm_NF : BinOpRM_R<BaseOpc2, mnemonic, Xi32>, NF;
704 def 32rm_EVEX : BinOpRM_RF<BaseOpc2, mnemonic, Xi32, null_frag>, PL;
713 def 32ri8 : BinOpRI8_RF<0x83, mnemonic, Xi32, RegMRM>, OpSize32;
717 def 32ri : BinOpRI_RF<0x81, mnemonic, Xi32, opnodeflag, RegMRM>, OpSize32;
722 def 32ri8_ND : BinOpRI8_RF<0x83, mnemonic, Xi32, RegMRM, 1>;
726 def 32ri_ND : BinOpRI_RF<0x81, mnemonic, Xi32, opnodeflag, RegMRM, 1>;
729 def 32ri8_NF_ND : BinOpRI8_R<0x83, mnemonic, Xi32, RegMRM, 1>, EVEX_NF;
733 def 32ri_NF_ND : BinOpRI_R<0x81, mnemonic, Xi32, RegMRM, 1>, EVEX_NF;
738 def 32ri8_NF : BinOpRI8_R<0x83, mnemonic, Xi32, RegMRM>, NF;
742 def 32ri_NF : BinOpRI_R<0x81, mnemonic, Xi32, RegMRM>, NF;
745 def 32ri8_EVEX : BinOpRI8_RF<0x83, mnemonic, Xi32, RegMRM>, PL;
749 def 32ri_EVEX : BinOpRI_RF<0x81, mnemonic, Xi32, null_frag, RegMRM>, PL;
756 def 32mr : BinOpMR_MF<BaseOpc, mnemonic, Xi32, opnode>, OpSize32;
762 def 32mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi32, node>;
766 def 32mr_NF_ND : BinOpMR_R<BaseOpc, mnemonic, Xi32>, EVEX_NF;
772 def 32mr_NF : BinOpMR_M<BaseOpc, mnemonic, Xi32>, NF;
776 def 32mr_EVEX : BinOpMR_MF<BaseOpc, mnemonic, Xi32, null_frag>, PL;
783 def 32mi8 : BinOpMI8_MF<mnemonic, Xi32, MemMRM>, OpSize32;
788 def 32mi : BinOpMI_MF<0x81, mnemonic, Xi32, opnode, MemMRM>, OpSize32;
793 def 32mi8_ND : BinOpMI8_RF<mnemonic, Xi32, MemMRM>;
797 def 32mi_ND : BinOpMI_RF<0x81, mnemonic, Xi32, opnode, MemMRM>;
800 def 32mi8_NF_ND : BinOpMI8_R<mnemonic, Xi32, MemMRM>, NF;
804 def 32mi_NF_ND : BinOpMI_R<0x81, mnemonic, Xi32, MemMRM>, NF;
809 def 32mi8_NF : BinOpMI8_M<mnemonic, Xi32, MemMRM>, NF;
813 def 32mi_NF : BinOpMI_M<0x81, mnemonic, Xi32, MemMRM>, NF;
816 def 32mi8_EVEX : BinOpMI8_MF<mnemonic, Xi32, MemMRM>, PL;
820 def 32mi_EVEX : BinOpMI_MF<0x81, mnemonic, Xi32, null_frag, MemMRM>, PL;
833 def 32i32 : BinOpAI_AF<BaseOpc4, mnemonic, Xi32, EAX, "{$src, %eax|eax, $src}">, OpSize32;
852 def 32rr : BinOpRRF_RF<BaseOpc, mnemonic, Xi32, opnode>, OpSize32;
860 def 32rr_ND : BinOpRRF_RF<BaseOpc, mnemonic, Xi32, opnode, 1>;
869 def 32rr_EVEX : BinOpRRF_RF<BaseOpc, mnemonic, Xi32, null_frag>, PL;
875 def 32rr_REV : BinOpRRF_RF_Rev<BaseOpc2, mnemonic, Xi32>, OpSize32;
880 def 32rr_ND_REV : BinOpRRF_RF_Rev<BaseOpc2, mnemonic, Xi32, 1>;
884 def 32rr_EVEX_REV : BinOpRRF_RF_Rev<BaseOpc2, mnemonic, Xi32>, PL;
891 def 32rm : BinOpRMF_RF<BaseOpc2, mnemonic, Xi32, opnode>, OpSize32;
897 def 32rm_ND : BinOpRMF_RF<BaseOpc2, mnemonic, Xi32, opnode, 1>;
903 def 32rm_EVEX : BinOpRMF_RF<BaseOpc2, mnemonic, Xi32, opnode>, PL;
913 def 32ri8 : BinOpRI8F_RF<0x83, mnemonic, Xi32, RegMRM>, OpSize32;
917 def 32ri : BinOpRIF_RF<0x81, mnemonic, Xi32, opnode, RegMRM>, OpSize32;
926 def 32ri8_ND : BinOpRI8F_RF<0x83, mnemonic, Xi32, RegMRM, 1>;
929 def 32ri_ND : BinOpRIF_RF<0x81, mnemonic, Xi32, opnode, RegMRM, 1>;
936 def 32ri8_EVEX : BinOpRI8F_RF<0x83, mnemonic, Xi32, RegMRM>, PL;
939 def 32ri_EVEX : BinOpRIF_RF<0x81, mnemonic, Xi32, opnode, RegMRM>, PL;
945 def 32mr : BinOpMRF_MF<BaseOpc, mnemonic, Xi32, opnode>, OpSize32;
951 def 32mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi32, node>;
957 def 32mr_EVEX : BinOpMRF_MF<BaseOpc, mnemonic, Xi32, null_frag>, PL;
965 def 32mi8 : BinOpMI8F_MF<mnemonic, Xi32, MemMRM>, OpSize32;
969 def 32mi : BinOpMIF_MF<0x81, mnemonic, Xi32, opnode, MemMRM>, OpSize32;
976 def 32mi8_ND : BinOpMI8F_RF<mnemonic, Xi32, MemMRM>;
979 def 32mi_ND : BinOpMIF_RF<0x81, mnemonic, Xi32, opnode, MemMRM>;
985 def 32mi8_EVEX : BinOpMI8F_MF<mnemonic, Xi32, MemMRM>, PL;
988 def 32mi_EVEX : BinOpMIF_MF<0x81, mnemonic, Xi32, opnode, MemMRM>, PL;
1001 def 32i32 : BinOpAIF_AF<BaseOpc4, mnemonic, Xi32, EAX, "{$src, %eax|eax, $src}">, OpSize32;
1017 def 32rr : BinOpRR_F<BaseOpc, mnemonic, Xi32, opnode>, OpSize32;
1024 def 32rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi32>, OpSize32;
1029 def 32rm : BinOpRM_F<BaseOpc2, mnemonic, Xi32, opnode>, OpSize32;
1038 def 32ri8 : BinOpRI8_F<0x83, mnemonic, Xi32, RegMRM>, OpSize32;
1042 def 32ri : BinOpRI_F<0x81, mnemonic, Xi32, opnode, RegMRM>, OpSize32;
1048 def 32mr : BinOpMR_F<BaseOpc, mnemonic, Xi32, opnode>, OpSize32;
1054 def 32mi8 : BinOpMI8_F<mnemonic, Xi32, MemMRM>, OpSize32;
1060 def 32mi : BinOpMI_F<0x81, mnemonic, Xi32, opnode, MemMRM>, OpSize32;
1074 def 32i32 : BinOpAI_F<BaseOpc4, mnemonic, Xi32, EAX, "{$src, %eax|eax, $src}">, OpSize32;
1156 (!cast<Instruction>(NAME#"32ri") GR32:$src1, relocImm32_su:$src2)>;
1165 (!cast<Instruction>(NAME#"32mi") addr:$dst, relocImm32_su:$src)>;
1175 (!cast<Instruction>(NAME#"32ri_ND") GR32:$src1, relocImm32_su:$src2)>;
1184 (!cast<Instruction>(NAME#"32mi_ND") addr:$dst, relocImm32_su:$src)>;
1197 (!cast<Instruction>(NAME#"32ri") GR32:$src1, relocImm32_su:$src2)>;
1206 (!cast<Instruction>(NAME#"32mi") addr:$dst, relocImm32_su:$src)>;
1216 (!cast<Instruction>(NAME#"32ri_ND") GR32:$src1, relocImm32_su:$src2)>;
1225 (!cast<Instruction>(NAME#"32mi_ND") addr:$dst, relocImm32_su:$src)>;
1237 (!cast<Instruction>(NAME#"32ri") GR32:$src1, relocImm32_su:$src2)>;
1246 (!cast<Instruction>(NAME#"32mi") addr:$src1, relocImm32_su:$src2)>;