Lines Matching refs:SrcInfo
1019 X86VectorVTInfo SrcInfo> {
1020 def : Pat<(DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
1022 (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>;
1024 (X86VBroadcast SrcInfo.FRC:$src),
1028 (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>;
1030 (X86VBroadcast SrcInfo.FRC:$src),
1033 DestInfo.KRCWM:$mask, (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>;
1042 X86VectorVTInfo SrcInfo,
1045 SDPatternOperator UnmaskedBcastOp = SrcInfo.BroadcastLdFrag> {
1047 def rr : AVX512PI<opc, MRMSrcReg, (outs MaskInfo.RC:$dst), (ins SrcInfo.RC:$src),
1053 (UnmaskedOp (SrcInfo.VT SrcInfo.RC:$src))))))],
1056 (ins MaskInfo.KRCWM:$mask, SrcInfo.RC:$src),
1064 (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))))),
1070 SrcInfo.RC:$src),
1078 (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))))),
1084 (ins SrcInfo.ScalarMemOp:$src),
1092 EVEX_CD8<SrcInfo.EltSize, CD8VT1>, Sched<[SchedRM]>;
1095 (ins MaskInfo.KRCWM:$mask, SrcInfo.ScalarMemOp:$src),
1103 (SrcInfo.BroadcastLdFrag addr:$src)))),
1106 EVEX_CD8<SrcInfo.EltSize, CD8VT1>, Sched<[SchedRM]>;
1112 SrcInfo.ScalarMemOp:$src),
1120 (SrcInfo.BroadcastLdFrag addr:$src)))),
1123 EVEX_CD8<SrcInfo.EltSize, CD8VT1>, Sched<[SchedRM]>;
1130 X86VectorVTInfo SrcInfo,
1133 DestInfo, DestInfo, SrcInfo,
9697 X86FoldableSchedWrite sched, X86VectorVTInfo SrcInfo,
9701 (ins SrcInfo.RC:$src),
9704 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src))))]>,
9708 (ins DestInfo.RC:$src0, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
9711 (MaskNode (SrcInfo.VT SrcInfo.RC:$src),
9713 SrcInfo.KRCWM:$mask))]>,
9716 (ins SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
9719 (DestInfo.VT (MaskNode (SrcInfo.VT SrcInfo.RC:$src),
9720 DestInfo.ImmAllZerosV, SrcInfo.KRCWM:$mask)))]>,
9726 (ins x86memop:$dst, SrcInfo.RC:$src),
9731 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
9737 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
9741 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
9742 (!cast<Instruction>(Name#SrcInfo.ZSuffix#mr)
9743 addr:$dst, SrcInfo.RC:$src)>;
9745 def : Pat<(mtruncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst,
9746 SrcInfo.KRCWM:$mask),
9747 (!cast<Instruction>(Name#SrcInfo.ZSuffix#mrk)
9748 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
9945 X86VectorVTInfo SrcInfo> {
9946 def : Pat<(DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src),
9948 SrcInfo.KRCWM:$mask)),
9950 SrcInfo.KRCWM:$mask,
9951 SrcInfo.RC:$src)>;
9953 def : Pat<(DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src),
9955 SrcInfo.KRCWM:$mask)),
9956 (!cast<Instruction>(InstrName#"rrkz") SrcInfo.KRCWM:$mask,
9957 SrcInfo.RC:$src)>;
9981 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
9985 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
9986 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
10742 X86VectorVTInfo SrcInfo>{
10745 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
10747 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
10748 (SrcInfo.VT SrcInfo.RC:$src2),
10752 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
10754 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
10755 (SrcInfo.VT (bitconvert
10756 (SrcInfo.LdFrag addr:$src2))),
10850 AVX512VLVectorVTInfo SrcInfo, Predicate Pred = HasBWI> {
10853 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX, VVVV;
10857 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX, VVVV;
10859 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX, VVVV;