Lines Matching refs:DestInfo
1018 multiclass avx512_broadcast_scalar<string Name, X86VectorVTInfo DestInfo,
1020 def : Pat<(DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
1021 (!cast<Instruction>(Name#DestInfo.ZSuffix#rr)
1023 def : Pat<(DestInfo.VT (vselect_mask DestInfo.KRCWM:$mask,
1025 DestInfo.RC:$src0)),
1026 (!cast<Instruction>(Name#DestInfo.ZSuffix#rrk)
1027 DestInfo.RC:$src0, DestInfo.KRCWM:$mask,
1029 def : Pat<(DestInfo.VT (vselect_mask DestInfo.KRCWM:$mask,
1031 DestInfo.ImmAllZerosV)),
1032 (!cast<Instruction>(Name#DestInfo.ZSuffix#rrkz)
1033 DestInfo.KRCWM:$mask, (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>;
1041 X86VectorVTInfo DestInfo,
1052 (DestInfo.VT
1054 DestInfo.ExeDomain>, T8, PD, EVEX, Sched<[SchedRR]>;
1063 (DestInfo.VT
1066 DestInfo.ExeDomain>, T8, PD, EVEX, EVEX_KZ, Sched<[SchedRR]>;
1077 (DestInfo.VT
1080 DestInfo.ExeDomain>, T8, PD, EVEX, EVEX_K, Sched<[SchedRR]>;
1089 (DestInfo.VT
1091 DestInfo.ExeDomain>, T8, PD, EVEX,
1102 (DestInfo.VT
1105 DestInfo.ExeDomain>, T8, PD, EVEX, EVEX_KZ,
1119 (DestInfo.VT
1122 DestInfo.ExeDomain>, T8, PD, EVEX, EVEX_K,
1129 X86VectorVTInfo DestInfo,
1133 DestInfo, DestInfo, SrcInfo,
9698 X86VectorVTInfo DestInfo, X86MemOperand x86memop> {
9699 let ExeDomain = DestInfo.ExeDomain in {
9700 def rr : AVX512XS8I<opc, MRMDestReg, (outs DestInfo.RC:$dst),
9703 [(set DestInfo.RC:$dst,
9704 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src))))]>,
9707 def rrk : AVX512XS8I<opc, MRMDestReg, (outs DestInfo.RC:$dst),
9708 (ins DestInfo.RC:$src0, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
9710 [(set DestInfo.RC:$dst,
9712 (DestInfo.VT DestInfo.RC:$src0),
9715 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs DestInfo.RC:$dst),
9718 [(set DestInfo.RC:$dst,
9719 (DestInfo.VT (MaskNode (SrcInfo.VT SrcInfo.RC:$src),
9720 DestInfo.ImmAllZerosV, SrcInfo.KRCWM:$mask)))]>,
9724 let mayStore = 1, hasSideEffects = 0, ExeDomain = DestInfo.ExeDomain in {
9944 X86VectorVTInfo DestInfo,
9946 def : Pat<(DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src),
9947 DestInfo.RC:$src0,
9949 (!cast<Instruction>(InstrName#"rrk") DestInfo.RC:$src0,
9953 def : Pat<(DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src),
9954 DestInfo.ImmAllZerosV,
9981 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
9983 let ExeDomain = DestInfo.ExeDomain in {
9984 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
9986 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
9989 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
9991 (DestInfo.VT (LdFrag addr:$src))>,
10741 X86FoldableSchedWrite sched, X86VectorVTInfo DestInfo,
10743 let ExeDomain = DestInfo.ExeDomain, ImmT = Imm8 in {
10744 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
10747 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
10751 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
10754 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
10849 X86SchedWriteWidths sched, AVX512VLVectorVTInfo DestInfo,
10852 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, sched.ZMM, DestInfo.info512,
10856 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, sched.XMM, DestInfo.info128,
10858 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, sched.YMM, DestInfo.info256,