Lines Matching full:tile
31 def TILELOADD#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
36 def TILELOADDT1#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
42 (ins sibmem:$dst, TILE:$src),
56 def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),
65 def PTILELOADDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
69 def PTILELOADDT1V : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
75 TILE:$src4), []>;
78 def PTILEZEROV : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2),
79 [(set TILE:$dst, (int_x86_tilezero_internal
83 // Pseudo instructions, using immediates instead of tile registers.
101 def TDPBSSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
102 (ins TILE:$src1, TILE:$src2, TILE:$src3),
105 def TDPBSUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
106 (ins TILE:$src1, TILE:$src2, TILE:$src3),
109 def TDPBUSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
110 (ins TILE:$src1, TILE:$src2, TILE:$src3),
113 def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
114 (ins TILE:$src1, TILE:$src2, TILE:$src3),
121 def PTDPBSSDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
122 GR16:$src2, GR16:$src3, TILE:$src4,
123 TILE:$src5, TILE:$src6),
124 [(set TILE: $dst,
126 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
127 def PTDPBSUDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
128 GR16:$src2, GR16:$src3, TILE:$src4,
129 TILE:$src5, TILE:$src6),
130 [(set TILE: $dst,
132 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
133 def PTDPBUSDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
134 GR16:$src2, GR16:$src3, TILE:$src4,
135 TILE:$src5, TILE:$src6),
136 [(set TILE: $dst,
138 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
139 def PTDPBUUDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
140 GR16:$src2, GR16:$src3, TILE:$src4,
141 TILE:$src5, TILE:$src6),
142 [(set TILE: $dst,
144 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
148 // Pseudo instructions, using immediates instead of tile registers.
173 def TDPBF16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
174 (ins TILE:$src1, TILE:$src2, TILE:$src3),
180 def PTDPBF16PSV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
181 GR16:$src2, GR16:$src3, TILE:$src4,
182 TILE:$src5, TILE:$src6),
183 [(set TILE: $dst,
185 GR16:$src2, GR16:$src3, TILE:$src4,
186 TILE:$src5, TILE:$src6))]>;
189 // Pseudo instructions, using immediates instead of tile registers.
203 def TDPFP16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
204 (ins TILE:$src1, TILE:$src2, TILE:$src3),
211 def PTDPFP16PSV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
212 GR16:$src2, GR16:$src3, TILE:$src4,
213 TILE:$src5, TILE:$src6),
214 [(set TILE: $dst,
216 GR16:$src2, GR16:$src3, TILE:$src4,
217 TILE:$src5, TILE:$src6))]>;
232 def TCMMIMFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),
233 (ins TILE:$src1, TILE:$src2, TILE:$src3),
236 def TCMMRLFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),
237 (ins TILE:$src1, TILE:$src2, TILE:$src3),
244 def PTCMMIMFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
245 GR16:$src2, GR16:$src3, TILE:$src4,
246 TILE:$src5, TILE:$src6),
247 [(set TILE: $dst,
249 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
250 def PTCMMRLFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
251 GR16:$src2, GR16:$src3, TILE:$src4,
252 TILE:$src5, TILE:$src6),
253 [(set TILE: $dst,
255 GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;