442   Value *Arg1 = II.getArgOperand(1);  in simplifyX86pack()  local
446   if (isa<UndefValue>(Arg0) && isa<UndefValue>(Arg1))  in simplifyX86pack()
462   if (!isa<Constant>(Arg0) || !isa<Constant>(Arg1))  in simplifyX86pack()
487   Arg1 = Builder.CreateSelect(Builder.CreateICmpSLT(Arg1, MinC), MinC, Arg1);  in simplifyX86pack()
489   Arg1 = Builder.CreateSelect(Builder.CreateICmpSGT(Arg1, MaxC), MaxC, Arg1);  in simplifyX86pack()
499   auto *Shuffle = Builder.CreateShuffleVector(Arg0, Arg1, PackMask);  in simplifyX86pack()
509   Value *Arg1 = II.getArgOperand(1);  in simplifyX86pmulh()  local
517   if (isa<UndefValue>(Arg0) || isa<UndefValue>(Arg1))  in simplifyX86pmulh()
521   if (isa<ConstantAggregateZero>(Arg0) || isa<ConstantAggregateZero>(Arg1))  in simplifyX86pmulh()
527       return IsSigned ? Builder.CreateAShr(Arg1, 15)  in simplifyX86pmulh()
529     if (match(Arg1, m_One()))  in simplifyX86pmulh()
535   if (!isa<Constant>(Arg0) || !isa<Constant>(Arg1))  in simplifyX86pmulh()
543   Value *RHS = Builder.CreateCast(Cast, Arg1, ExtTy);  in simplifyX86pmulh()
567   Value *Arg1 = II.getArgOperand(1);  in simplifyX86pmadd()  local
577   if (isa<UndefValue>(Arg0) || isa<UndefValue>(Arg1))  in simplifyX86pmadd()
581   if (isa<ConstantAggregateZero>(Arg0) || isa<ConstantAggregateZero>(Arg1))  in simplifyX86pmadd()
585   if (!isa<Constant>(Arg0) || !isa<Constant>(Arg1))  in simplifyX86pmadd()
601   auto *RHSLo = Builder.CreateShuffleVector(Arg1, LoMask);  in simplifyX86pmadd()
602   auto *RHSHi = Builder.CreateShuffleVector(Arg1, HiMask);  in simplifyX86pmadd()
2373     Value *Arg1 = II.getArgOperand(1);  in instCombineIntrinsic()  local
2379     if (Value *V = SimplifyDemandedVectorEltsLow(Arg1, VWidth, 1)) {  in instCombineIntrinsic()
2402         Value *Arg1 = II.getArgOperand(1);  in instCombineIntrinsic()  local
2410           V = IC.Builder.CreateFAdd(Arg0, Arg1);  in instCombineIntrinsic()
2414           V = IC.Builder.CreateFSub(Arg0, Arg1);  in instCombineIntrinsic()
2418           V = IC.Builder.CreateFMul(Arg0, Arg1);  in instCombineIntrinsic()
2422           V = IC.Builder.CreateFDiv(Arg0, Arg1);  in instCombineIntrinsic()
2445         Value *Arg1 = II.getArgOperand(1);  in instCombineIntrinsic()  local
2447         Value *RHS = IC.Builder.CreateExtractElement(Arg1, (uint64_t)0);  in instCombineIntrinsic()
2564     Value *Arg1 = II.getArgOperand(1);  in instCombineIntrinsic()  local
2565     assert(Arg1->getType()->getPrimitiveSizeInBits() == 128 &&  in instCombineIntrinsic()
2567     unsigned VWidth = cast<FixedVectorType>(Arg1->getType())->getNumElements();  in instCombineIntrinsic()
2569     if (Value *V = SimplifyDemandedVectorEltsLow(Arg1, VWidth, VWidth / 2)) {  in instCombineIntrinsic()
2677       Value *Arg1 = II.getArgOperand(1);  in instCombineIntrinsic()  local
2694               IC.SimplifyDemandedVectorElts(Arg1, DemandedElts2, UndefElts2)) {  in instCombineIntrinsic()
3246       Value *Arg0 = II.getArgOperand(0), *Arg1 = II.getArgOperand(1);  in simplifyDemandedVectorEltsIntrinsic()  local
3248           IsSubOnly ? Instruction::FSub : Instruction::FAdd, Arg0, Arg1);  in simplifyDemandedVectorEltsIntrinsic()