Lines Matching refs:VZEXT_MOVL
2726 case X86ISD::VZEXT_MOVL: in isTargetShuffle()
4954 if (Op.getOpcode() == X86ISD::VZEXT_MOVL && in getTargetConstantBitsFromNode()
5365 case X86ISD::VZEXT_MOVL: in getTargetShuffleMask()
6570 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v4i32, V); in LowerBuildVectorv16i8()
12162 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V); in lowerShuffleAsZeroOrAnyExtend()
12276 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2)); in lowerShuffleAsElementInsertion()
12314 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2); in lowerShuffleAsElementInsertion()
25270 ShAmt = DAG.getNode(X86ISD::VZEXT_MOVL, dl, MVT::v4i32, ShAmt); in getTargetVShiftNode()
25301 ShAmt = DAG.getNode(X86ISD::VZEXT_MOVL, SDLoc(ShAmt), MVT::v4i32, ShAmt); in getTargetVShiftNode()
33768 NODE_NAME_CASE(VZEXT_MOVL) in getTargetNodeName()
37837 Shuffle = X86ISD::VZEXT_MOVL; in matchUnaryShuffle()
37896 Shuffle = X86ISD::VZEXT_MOVL; in matchUnaryShuffle()
40938 case X86ISD::VZEXT_MOVL: { in combineTargetShuffle()
40984 SDValue Movl = DAG.getNode(X86ISD::VZEXT_MOVL, DL, VecVT, SclVec); in combineTargetShuffle()
41027 SDValue Movl = DAG.getNode(X86ISD::VZEXT_MOVL, DL, SubVT, In); in combineTargetShuffle()
42314 case X86ISD::VZEXT_MOVL: { in SimplifyDemandedVectorEltsForTargetNode()
42500 case X86ISD::VZEXT_MOVL: in SimplifyDemandedVectorEltsForTargetNode()
57253 DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v4i32, in combineScalarToVector()
57894 case X86ISD::VZEXT_MOVL: in PerformDAGCombine()