4661       LHS = DAG.getNode(X86ISD::VSRLI, dl, OpVT, LHS, Amt);  in getPack()
4662       RHS = DAG.getNode(X86ISD::VSRLI, dl, OpVT, RHS, Amt);  in getPack()
6169   case X86ISD::VSRLI: {  in getFauxShuffleMask()
10276             X86ISD::VSRLI, DL, SrcVT, Src,  in lowerShuffleAsVTRUNC()
11323     SDValue SRL = DAG.getNode(X86ISD::VSRLI, DL, RotateVT, V1,  in lowerShuffleAsBitRotate()
11668                   : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);  in matchShuffleAsShift()
14042     V1 = DAG.getNode(HasSSE41 ? X86ISD::VSRLI : X86ISD::VSRAI, DL, MVT::v4i32,  in lowerV8I16Shuffle()
14045     V2 = DAG.getNode(HasSSE41 ? X86ISD::VSRLI : X86ISD::VSRAI, DL, MVT::v4i32,  in lowerV8I16Shuffle()
14432     V1 = DAG.getNode(X86ISD::VSRLI, DL, MVT::v8i16,  in lowerV16I8Shuffle()
14436       V2 = DAG.getNode(X86ISD::VSRLI, DL, MVT::v8i16,  in lowerV16I8Shuffle()
25169   case X86ISD::VSRLI:  in getTargetVShiftUniformOpcode()
25170     return IsVariable ? X86ISD::VSRL : X86ISD::VSRLI;  in getTargetVShiftUniformOpcode()
25203   assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)  in getTargetVShiftByConstNode()
25215     case X86ISD::VSRLI:  in getTargetVShiftByConstNode()
28612     SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);  in LowerMUL()
28618     SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);  in LowerMUL()
28806     Mul = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExVT, Mul, 8, DAG);  in LowerMULH()
28891         High = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExVT, Mul, 8, DAG);  in LowerMULO()
28900           getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExVT, Mul, 8, DAG);  in LowerMULO()
29220           getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);  in LowerShiftByScalarImmediate()
29322       SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT, R,  in LowerShiftByScalarImmediate()
29720       R = DAG.getNode(X86ISD::VSRLI, dl, ExVT, R, Cst8);  in LowerShift()
29742     LoR = DAG.getNode(X86ISD::VSRLI, dl, VT16, LoR, Cst8);  in LowerShift()
29743     HiR = DAG.getNode(X86ISD::VSRLI, dl, VT16, HiR, Cst8);  in LowerShift()
29850       RLo = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, RLo, 8, DAG);  in LowerShift()
29851       RHi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, RHi, 8, DAG);  in LowerShift()
29869     Lo = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, Lo, 16, DAG);  in LowerShift()
29870     Hi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExtVT, Hi, 16, DAG);  in LowerShift()
30087         Res = getTargetVShiftByConstNode(X86ISD::VSRLI, DL, WideVT, Res,  in LowerFunnelShift()
30279       unsigned ShiftX86Opc = IsROTL ? X86ISD::VSHLI : X86ISD::VSRLI;  in LowerRotate()
30332         R = getTargetVShiftByConstNode(X86ISD::VSRLI, DL, WideVT, R, 8, DAG);  in LowerRotate()
33798   NODE_NAME_CASE(VSRLI)  in getTargetNodeName()
37244   case X86ISD::VSRLI: {  in computeKnownBitsForTargetNode()
37263     } else if (Opc == X86ISD::VSRLI) {  in computeKnownBitsForTargetNode()
40674   case X86ISD::VSRLI:  in canonicalizeLaneShuffleWithRepeatedOps()
41232       case X86ISD::VSRLI:  in combineTargetShuffle()
41986   case X86ISD::VSRLI:  in SimplifyDemandedVectorEltsForTargetNode()
42455     case X86ISD::VSRLI:  in SimplifyDemandedVectorEltsForTargetNode()
42752     if (Op0.getOpcode() == X86ISD::VSRLI &&  in SimplifyDemandedBitsForTargetNode()
42760         unsigned NewOpc = Diff < 0 ? X86ISD::VSRLI : X86ISD::VSHLI;  in SimplifyDemandedBitsForTargetNode()
42786   case X86ISD::VSRLI: {  in SimplifyDemandedBitsForTargetNode()
42845           Op, TLO.DAG.getNode(X86ISD::VSRLI, SDLoc(Op), VT, Op0, Op1));  in SimplifyDemandedBitsForTargetNode()
43329   case X86ISD::VSRLI:  in canCreateUndefOrPoisonForTargetNode()
47798       return DAG.getNode(X86ISD::VSRLI, DL, VT, Op.getOperand(0),  in combineMulToPMADDWD()
48694           X86ISD::VSRLI == Opcode) &&  in combineVectorShiftImm()
48696   bool LogicalShift = X86ISD::VSHLI == Opcode || X86ISD::VSRLI == Opcode;  in combineVectorShiftImm()
49326   case X86ISD::VSRLI:  in combineBitOpWithShift()
49444   SDValue Shift = DAG.getNode(X86ISD::VSRLI, DL, VT, Op0, ShAmt);  in combineAndMaskToShift()
56418     case X86ISD::VSRLI:  in combineConcatVectorOps()
57190   if ((InOpcode == X86ISD::VSHLI || InOpcode == X86ISD::VSRLI) &&  in combineEXTRACT_SUBVECTOR()
57856   case X86ISD::VSRLI:  in PerformDAGCombine()