Lines Matching refs:VSHLI
4672 LHS = DAG.getNode(X86ISD::VSHLI, dl, OpVT, LHS, Amt); in getPack()
4673 RHS = DAG.getNode(X86ISD::VSHLI, dl, OpVT, RHS, Amt); in getPack()
6168 case X86ISD::VSHLI: in getFauxShuffleMask()
6187 if (X86ISD::VSHLI == Opcode) { in getFauxShuffleMask()
11321 SDValue SHL = DAG.getNode(X86ISD::VSHLI, DL, RotateVT, V1, in lowerShuffleAsBitRotate()
11667 Opcode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI) in matchShuffleAsShift()
14021 V1 = DAG.getNode(X86ISD::VSHLI, DL, MVT::v4i32, V1, ShAmt); in lowerV8I16Shuffle()
14022 V2 = DAG.getNode(X86ISD::VSHLI, DL, MVT::v4i32, V2, ShAmt); in lowerV8I16Shuffle()
25165 case X86ISD::VSHLI: in getTargetVShiftUniformOpcode()
25166 return IsVariable ? X86ISD::VSHL : X86ISD::VSHLI; in getTargetVShiftUniformOpcode()
25203 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI) in getTargetVShiftByConstNode()
25212 case X86ISD::VSHLI: in getTargetVShiftByConstNode()
28511 RHi = DAG.getNode(X86ISD::VSHLI, dl, ExVT, RHi, in LowerMUL()
28623 Hi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Hi, 32, DAG); in LowerMUL()
28880 getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ExVT, Mul, 8, DAG); in LowerMULO()
29313 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT, R, in LowerShiftByScalarImmediate()
29785 Amt = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ExtVT, Amt, 5, DAG); in LowerShift()
29905 getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Amt, 4, DAG), in LowerShift()
29906 getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Amt, 12, DAG)); in LowerShift()
29908 Amt = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Amt, 12, DAG); in LowerShift()
30082 Op0 = getTargetVShiftByConstNode(X86ISD::VSHLI, DL, WideVT, Op0, in LowerFunnelShift()
30279 unsigned ShiftX86Opc = IsROTL ? X86ISD::VSHLI : X86ISD::VSRLI; in LowerRotate()
30328 getTargetVShiftByConstNode(X86ISD::VSHLI, DL, WideVT, R, 8, DAG)); in LowerRotate()
33797 NODE_NAME_CASE(VSHLI) in getTargetNodeName()
37243 case X86ISD::VSHLI: in computeKnownBitsForTargetNode()
37258 if (Opc == X86ISD::VSHLI) { in computeKnownBitsForTargetNode()
37696 case X86ISD::VSHLI: { in ComputeNumSignBitsForTargetNode()
40673 case X86ISD::VSHLI: in canonicalizeLaneShuffleWithRepeatedOps()
41231 case X86ISD::VSHLI: in combineTargetShuffle()
41985 case X86ISD::VSHLI: in SimplifyDemandedVectorEltsForTargetNode()
42454 case X86ISD::VSHLI: in SimplifyDemandedVectorEltsForTargetNode()
42740 case X86ISD::VSHLI: { in SimplifyDemandedBitsForTargetNode()
42760 unsigned NewOpc = Diff < 0 ? X86ISD::VSRLI : X86ISD::VSHLI; in SimplifyDemandedBitsForTargetNode()
42819 if (Op0.getOpcode() == X86ISD::VSHLI && in SimplifyDemandedBitsForTargetNode()
43182 case X86ISD::VSHLI: { in SimplifyMultipleUseDemandedBitsForTargetNode()
43328 case X86ISD::VSHLI: in canCreateUndefOrPoisonForTargetNode()
48693 assert((X86ISD::VSHLI == Opcode || X86ISD::VSRAI == Opcode || in combineVectorShiftImm()
48696 bool LogicalShift = X86ISD::VSHLI == Opcode || X86ISD::VSRLI == Opcode; in combineVectorShiftImm()
48752 if (Opcode == X86ISD::VSHLI && N0.getOpcode() == ISD::ADD && in combineVectorShiftImm()
48772 if (BC.getOpcode() == X86ISD::VSHLI && in combineVectorShiftImm()
48780 Src = DAG.getNode(X86ISD::VSHLI, DL, VT, Src, N1); in combineVectorShiftImm()
48802 else if (X86ISD::VSHLI == Opcode) in combineVectorShiftImm()
49325 case X86ISD::VSHLI: in combineBitOpWithShift()
54568 ShiftLHS = getTargetVShiftByConstNode(X86ISD::VSHLI, DL, ShiftVT, in combineMOVMSK()
54570 ShiftRHS = getTargetVShiftByConstNode(X86ISD::VSHLI, DL, ShiftVT, in combineMOVMSK()
56417 case X86ISD::VSHLI: in combineConcatVectorOps()
56427 if (Op0.getOpcode() == X86ISD::VSHLI) { in combineConcatVectorOps()
57190 if ((InOpcode == X86ISD::VSHLI || InOpcode == X86ISD::VSRLI) && in combineEXTRACT_SUBVECTOR()
57854 case X86ISD::VSHLI: in PerformDAGCombine()