2714   case X86ISD::UNPCKL:  in isTargetShuffle()
5293   case X86ISD::UNPCKL:  in getTargetShuffleMask()
9941     UnpackOpcode = X86ISD::UNPCKL;  in matchShuffleWithUNPCK()
9977       UnpackOpcode = MatchLo ? X86ISD::UNPCKL : X86ISD::UNPCKH;  in matchShuffleWithUNPCK()
9988       UnpackOpcode = X86ISD::UNPCKL;  in matchShuffleWithUNPCK()
10012     return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);  in lowerShuffleWithUNPCK()
10022     return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);  in lowerShuffleWithUNPCK()
10042     UnpackOpcode = X86ISD::UNPCKL;  in lowerShuffleWithUNPCK256()
10914   unsigned UnpckOp = MatchLo ? X86ISD::UNPCKL : X86ISD::UNPCKH;  in lowerShuffleAsUNPCKAndPermute()
10988         VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,  in lowerShuffleAsPermuteAndUnpack()
11029         DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL, DL, VT,  in lowerShuffleAsPermuteAndUnpack()
11987                           DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));  in lowerShuffleAsSpecificZeroOrAnyExtend()
12024     unsigned UnpackLoHi = X86ISD::UNPCKL;  in lowerShuffleAsSpecificZeroOrAnyExtend()
14280       V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,  in lowerV16I8Shuffle()
14486         MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));  in lowerV16I8Shuffle()
15809   SDValue Unpckl = DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);  in lowerShufflePairAsUNPCKAndPermute()
33855   NODE_NAME_CASE(UNPCKL)  in getTargetNodeName()
38141       Shuffle = Subtarget.hasSSE2() ? X86ISD::UNPCKL : X86ISD::MOVLHPS;  in matchBinaryShuffle()
40238     case X86ISD::UNPCKL:  in combineRedundantDWordShuffle()
40248           V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;  in combineRedundantDWordShuffle()
40301     case X86ISD::UNPCKL:  in combineRedundantDWordShuffle()
40574   case X86ISD::UNPCKL: {  in canonicalizeShuffleWithOp()
41475           return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL  in combineTargetShuffle()
42510     case X86ISD::UNPCKL:  in SimplifyDemandedVectorEltsForTargetNode()
43335   case X86ISD::UNPCKL:  in canCreateUndefOrPoisonForTargetNode()
56213           return DAG.getNode(X86ISD::UNPCKL, DL, VT,  in combineConcatVectorOps()
56246     case X86ISD::UNPCKL: {  in combineConcatVectorOps()
57871   case X86ISD::UNPCKL:  in PerformDAGCombine()