Lines Matching refs:SubVec
4330 SDValue SubVec = Op.getOperand(1); in insert1BitVector() local
4335 if (SubVec.isUndef()) in insert1BitVector()
4354 SubVec, Idx); in insert1BitVector()
4358 MVT SubVecVT = SubVec.getSimpleValueType(); in insert1BitVector()
4374 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
4376 SubVec, ZeroIdx); in insert1BitVector()
4377 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec); in insert1BitVector()
4381 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
4382 Undef, SubVec, ZeroIdx); in insert1BitVector()
4386 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
4388 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx); in insert1BitVector()
4396 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
4402 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
4405 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec, in insert1BitVector()
4408 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx); in insert1BitVector()
4413 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
4431 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec); in insert1BitVector()
4452 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
4454 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec, in insert1BitVector()
4456 Op = DAG.getNode(ISD::OR, dl, WideOpVT, Vec, SubVec); in insert1BitVector()
4463 SubVec = DAG.getNode(X86ISD::KSHIFTL, dl, WideOpVT, SubVec, in insert1BitVector()
4465 SubVec = DAG.getNode(X86ISD::KSHIFTR, dl, WideOpVT, SubVec, in insert1BitVector()
4484 SubVec = DAG.getNode(ISD::OR, dl, WideOpVT, SubVec, Vec); in insert1BitVector()
4487 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx); in insert1BitVector()
9228 SDValue SubVec = Op.getOperand(i); in LowerAVXCONCAT_VECTORS() local
9229 if (SubVec.isUndef()) in LowerAVXCONCAT_VECTORS()
9231 if (ISD::isFreezeUndef(SubVec.getNode())) { in LowerAVXCONCAT_VECTORS()
9233 if (SubVec.hasOneUse()) in LowerAVXCONCAT_VECTORS()
9238 else if (ISD::isBuildVectorAllZeros(SubVec.getNode())) in LowerAVXCONCAT_VECTORS()
9294 SDValue SubVec = Op.getOperand(i); in LowerCONCAT_VECTORSvXi1() local
9295 if (SubVec.isUndef()) in LowerCONCAT_VECTORSvXi1()
9298 if (ISD::isBuildVectorAllZeros(SubVec.getNode())) in LowerCONCAT_VECTORSvXi1()
9312 SDValue SubVec = Op.getOperand(Idx); in LowerCONCAT_VECTORSvXi1() local
9313 unsigned SubVecNumElts = SubVec.getSimpleValueType().getVectorNumElements(); in LowerCONCAT_VECTORSvXi1()
9315 Op = widenSubVector(ShiftVT, SubVec, false, Subtarget, DAG, dl); in LowerCONCAT_VECTORSvXi1()
9328 SDValue SubVec = Op.getOperand(Idx); in LowerCONCAT_VECTORSvXi1() local
9329 unsigned SubVecNumElts = SubVec.getSimpleValueType().getVectorNumElements(); in LowerCONCAT_VECTORSvXi1()
9330 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, SubVec, in LowerCONCAT_VECTORSvXi1()
15004 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, in lowerV2X128Shuffle() local
15007 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec, in lowerV2X128Shuffle()
16676 SDValue SubVec = in lowerV4X128Shuffle() local
16679 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec, in lowerV4X128Shuffle()
49607 SDValue SubVec = Src.getOperand(0); in combineScalarAndWithMaskSetcc() local
49608 EVT SubVecVT = SubVec.getValueType(); in combineScalarAndWithMaskSetcc()
49628 if (!(IsLegalSetCC(SubVec) || (SubVec.getOpcode() == ISD::AND && in combineScalarAndWithMaskSetcc()
49629 (IsLegalSetCC(SubVec.getOperand(0)) || in combineScalarAndWithMaskSetcc()
49630 IsLegalSetCC(SubVec.getOperand(1)))))) in combineScalarAndWithMaskSetcc()
49638 Ops[0] = SubVec; in combineScalarAndWithMaskSetcc()
56788 SDValue SubVec = N->getOperand(1); in combineINSERT_SUBVECTOR() local
56791 MVT SubVecVT = SubVec.getSimpleValueType(); in combineINSERT_SUBVECTOR()
56793 if (Vec.isUndef() && SubVec.isUndef()) in combineINSERT_SUBVECTOR()
56798 (SubVec.isUndef() || ISD::isBuildVectorAllZeros(SubVec.getNode()))) in combineINSERT_SUBVECTOR()
56804 if (SubVec.getOpcode() == ISD::INSERT_SUBVECTOR && in combineINSERT_SUBVECTOR()
56805 ISD::isBuildVectorAllZeros(SubVec.getOperand(0).getNode())) { in combineINSERT_SUBVECTOR()
56806 uint64_t Idx2Val = SubVec.getConstantOperandVal(2); in combineINSERT_SUBVECTOR()
56809 SubVec.getOperand(1), in combineINSERT_SUBVECTOR()
56817 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR && IdxVal == 0 && in combineINSERT_SUBVECTOR()
56818 isNullConstant(SubVec.getOperand(1)) && in combineINSERT_SUBVECTOR()
56819 SubVec.getOperand(0).getOpcode() == ISD::INSERT_SUBVECTOR) { in combineINSERT_SUBVECTOR()
56820 SDValue Ins = SubVec.getOperand(0); in combineINSERT_SUBVECTOR()
56840 if (SubVec.getOpcode() == ISD::INSERT_SUBVECTOR && in combineINSERT_SUBVECTOR()
56841 SubVec.getOperand(0).isUndef() && isNullConstant(SubVec.getOperand(2))) in combineINSERT_SUBVECTOR()
56843 SubVec.getOperand(1), N->getOperand(2)); in combineINSERT_SUBVECTOR()
56847 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR && in combineINSERT_SUBVECTOR()
56848 SubVec.getOperand(0).getSimpleValueType() == OpVT && in combineINSERT_SUBVECTOR()
56851 int ExtIdxVal = SubVec.getConstantOperandVal(1); in combineINSERT_SUBVECTOR()
56863 return DAG.getVectorShuffle(OpVT, dl, Vec, SubVec.getOperand(0), Mask); in combineINSERT_SUBVECTOR()
56896 if (Vec.isUndef() && IdxVal != 0 && SubVec.getOpcode() == X86ISD::VBROADCAST) in combineINSERT_SUBVECTOR()
56897 return DAG.getNode(X86ISD::VBROADCAST, dl, OpVT, SubVec.getOperand(0)); in combineINSERT_SUBVECTOR()
56901 if (Vec.isUndef() && IdxVal != 0 && SubVec.hasOneUse() && in combineINSERT_SUBVECTOR()
56902 SubVec.getOpcode() == X86ISD::VBROADCAST_LOAD) { in combineINSERT_SUBVECTOR()
56903 auto *MemIntr = cast<MemIntrinsicSDNode>(SubVec); in combineINSERT_SUBVECTOR()
56916 if (IdxVal == (OpVT.getVectorNumElements() / 2) && SubVec.hasOneUse() && in combineINSERT_SUBVECTOR()
56917 Vec.getValueSizeInBits() == (2 * SubVec.getValueSizeInBits())) { in combineINSERT_SUBVECTOR()
56919 auto *SubLd = dyn_cast<LoadSDNode>(SubVec); in combineINSERT_SUBVECTOR()
56922 SubVec.getValueSizeInBits() / 8, 0)) in combineINSERT_SUBVECTOR()