Lines Matching refs:SSECC
23048 unsigned SSECC; in translateX86FSETCC() local
23064 case ISD::SETEQ: SSECC = 0; break; in translateX86FSETCC()
23068 case ISD::SETOLT: SSECC = 1; break; in translateX86FSETCC()
23072 case ISD::SETOLE: SSECC = 2; break; in translateX86FSETCC()
23073 case ISD::SETUO: SSECC = 3; break; in translateX86FSETCC()
23075 case ISD::SETNE: SSECC = 4; break; in translateX86FSETCC()
23077 case ISD::SETUGE: SSECC = 5; break; in translateX86FSETCC()
23079 case ISD::SETUGT: SSECC = 6; break; in translateX86FSETCC()
23080 case ISD::SETO: SSECC = 7; break; in translateX86FSETCC()
23081 case ISD::SETUEQ: SSECC = 8; break; in translateX86FSETCC()
23082 case ISD::SETONE: SSECC = 12; break; in translateX86FSETCC()
23104 return SSECC; in translateX86FSETCC()
23290 unsigned SSECC = translateX86FSETCC(Cond, Op0, Op1, IsAlwaysSignaling); in LowerVSETCC() local
23353 {Chain, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)}); in LowerVSETCC()
23357 Opc, dl, VT, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)); in LowerVSETCC()
23363 SSECC |= (IsAlwaysSignaling ^ IsSignaling) << 4; in LowerVSETCC()
23366 {Chain, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)}); in LowerVSETCC()
23370 Opc, dl, VT, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)); in LowerVSETCC()
24064 unsigned SSECC = in LowerSELECT() local
24071 DAG.getTargetConstant(SSECC, DL, MVT::i8)); in LowerSELECT()
24076 if (SSECC < 8 || Subtarget.hasAVX()) { in LowerSELECT()
24078 DAG.getTargetConstant(SSECC, DL, MVT::i8)); in LowerSELECT()