10496   MVT LogicVT = VT;  in lowerShuffleAsBitMask()  local
10502     LogicVT =  in lowerShuffleAsBitMask()
10527   VMask = DAG.getBitcast(LogicVT, VMask);  in lowerShuffleAsBitMask()
10528   V = DAG.getBitcast(LogicVT, V);  in lowerShuffleAsBitMask()
10529   SDValue And = DAG.getNode(ISD::AND, DL, LogicVT, V, VMask);  in lowerShuffleAsBitMask()
21861   MVT LogicVT = VT;  in LowerFABSorFNEG()  local
21863     LogicVT = (VT == MVT::f64)   ? MVT::v2f64  in LowerFABSorFNEG()
21872   SDValue Mask = DAG.getConstantFP(APFloat(Sem, MaskElt), dl, LogicVT);  in LowerFABSorFNEG()
21882     return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);  in LowerFABSorFNEG()
21886   Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);  in LowerFABSorFNEG()
21887   SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);  in LowerFABSorFNEG()
21922   MVT LogicVT = VT;  in LowerFCOPYSIGN()  local
21924     LogicVT = (VT == MVT::f64)   ? MVT::v2f64  in LowerFCOPYSIGN()
21931       APFloat(Sem, APInt::getSignMask(EltSizeInBits)), dl, LogicVT);  in LowerFCOPYSIGN()
21933       APFloat(Sem, APInt::getSignedMaxValue(EltSizeInBits)), dl, LogicVT);  in LowerFCOPYSIGN()
21937     Sign = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Sign);  in LowerFCOPYSIGN()
21938   SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Sign, SignMask);  in LowerFCOPYSIGN()
21947     MagBits = DAG.getConstantFP(APF, dl, LogicVT);  in LowerFCOPYSIGN()
21951       Mag = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Mag);  in LowerFCOPYSIGN()
21952     MagBits = DAG.getNode(X86ISD::FAND, dl, LogicVT, Mag, MagMask);  in LowerFCOPYSIGN()
21956   SDValue Or = DAG.getNode(X86ISD::FOR, dl, LogicVT, MagBits, SignBit);  in LowerFCOPYSIGN()