Lines Matching refs:DCI
40694 TargetLowering::DAGCombinerInfo &DCI, in combineTargetShuffle() argument
40714 DCI.CombineTo(N.getNode(), Movddup); in combineTargetShuffle()
40716 DCI.recursivelyDeleteUnusedNodes(LN); in combineTargetShuffle()
40815 DCI.CombineTo(N.getNode(), BcastLd); in combineTargetShuffle()
40818 DCI.recursivelyDeleteUnusedNodes(LN); in combineTargetShuffle()
40822 DCI.CombineTo(LN, Scl, BcastLd.getValue(1)); in combineTargetShuffle()
40846 DCI.CombineTo(N.getNode(), BcastLd); in combineTargetShuffle()
40848 DCI.recursivelyDeleteUnusedNodes(Src.getNode()); in combineTargetShuffle()
40863 DCI.CombineTo(N.getNode(), BcastLd); in combineTargetShuffle()
40865 DCI.recursivelyDeleteUnusedNodes(Src.getNode()); in combineTargetShuffle()
40892 DCI.CombineTo(N.getNode(), BcastLd); in combineTargetShuffle()
40894 DCI.recursivelyDeleteUnusedNodes(Src.getNode()); in combineTargetShuffle()
40909 DCI.CombineTo(N.getNode(), BcastLd); in combineTargetShuffle()
40911 DCI.recursivelyDeleteUnusedNodes(LN); in combineTargetShuffle()
40929 DCI.CombineTo(N.getNode(), BcastLd); in combineTargetShuffle()
40931 DCI.recursivelyDeleteUnusedNodes(LN); in combineTargetShuffle()
40947 DCI.CombineTo(N.getNode(), VZLoad); in combineTargetShuffle()
40949 DCI.recursivelyDeleteUnusedNodes(LN); in combineTargetShuffle()
40965 DCI.CombineTo(N.getNode(), VZLoad); in combineTargetShuffle()
40967 DCI.recursivelyDeleteUnusedNodes(LN); in combineTargetShuffle()
41017 if (!DCI.isBeforeLegalizeOps() && N0.hasOneUse()) { in combineTargetShuffle()
41753 TargetLowering::DAGCombinerInfo &DCI, in combineShuffle() argument
41785 if (SDValue Shuffle = combineTargetShuffle(Op, dl, DAG, DCI, Subtarget)) in combineShuffle()
41799 if (TLI.SimplifyDemandedVectorElts(Op, DemandedElts, DCI)) in combineShuffle()
43637 TargetLowering::DAGCombinerInfo &DCI, in combineCastedMaskArithmetic() argument
43641 if (!DCI.isBeforeLegalizeOps()) in combineCastedMaskArithmetic()
43862 TargetLowering::DAGCombinerInfo &DCI, in combineBitcast() argument
43875 if (DCI.isBeforeLegalize()) { in combineBitcast()
44099 if (SDValue V = combineCastedMaskArithmetic(N, DAG, DCI, Subtarget)) in combineBitcast()
44648 TargetLowering::DAGCombinerInfo &DCI) { in combineExtractFromVectorLoad() argument
44665 DCI.isAfterLegalizeDAG() && !LikelyUsedAsVector && LoadVec->isSimple()) { in combineExtractFromVectorLoad()
44684 TargetLowering::DAGCombinerInfo &DCI, in combineExtractWithShuffle() argument
44686 if (DCI.isBeforeLegalizeOps()) in combineExtractWithShuffle()
44879 N, SrcVT, peekThroughBitcasts(SrcOp), ExtractIdx, dl, DAG, DCI)) in combineExtractWithShuffle()
45182 TargetLowering::DAGCombinerInfo &DCI, in combineExtractVectorElt() argument
45184 if (SDValue NewOp = combineExtractWithShuffle(N, DAG, DCI, Subtarget)) in combineExtractVectorElt()
45232 DCI)) in combineExtractVectorElt()
45294 dl, DAG, DCI)) in combineExtractVectorElt()
45335 DCI.CombineTo(Use, Res); in combineExtractVectorElt()
45346 if (DCI.isBeforeLegalize() && TLI.isTypeLegal(TruncSVT)) { in combineExtractVectorElt()
45360 TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget) { in combineToExtendBoolVectorInReg() argument
45364 if (!DCI.isBeforeLegalizeOps()) in combineToExtendBoolVectorInReg()
45459 TargetLowering::DAGCombinerInfo &DCI, in combineVSelectWithAllOnesOrZeros() argument
45670 TargetLowering::DAGCombinerInfo &DCI, in combineVSelectToBLENDV() argument
45729 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in combineVSelectToBLENDV()
45730 !DCI.isBeforeLegalizeOps()); in combineVSelectToBLENDV()
45746 DCI.AddToWorklist(U); in combineVSelectToBLENDV()
45748 DCI.CommitTargetLoweringOpt(TLO); in combineVSelectToBLENDV()
45854 TargetLowering::DAGCombinerInfo &DCI, in combineSelect() argument
45890 if (CondConstantVector && DCI.isBeforeLegalizeOps() && in combineSelect()
46248 ISD::SIGN_EXTEND, DL, ExtCondVT, Cond, DAG, DCI, Subtarget)) { in combineSelect()
46294 if (SDValue V = combineVSelectWithAllOnesOrZeros(N, DAG, DL, DCI, Subtarget)) in combineSelect()
46297 if (SDValue V = combineVSelectToBLENDV(N, DAG, DL, DCI, Subtarget)) in combineSelect()
46327 (DCI.isBeforeLegalize() || (VT != MVT::v64i1 || Subtarget.is64Bit()))) { in combineSelect()
46329 if (DCI.isBeforeLegalize() || TLI.isTypeLegal(IntVT)) { in combineSelect()
46356 if (DCI.isBeforeLegalize() && !Subtarget.hasAVX512() && in combineSelect()
47240 TargetLowering::DAGCombinerInfo &DCI, in combineCMov() argument
47364 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { in combineCMov()
47865 TargetLowering::DAGCombinerInfo &DCI, in combineMul() argument
47876 if (DCI.isBeforeLegalize() && VT.isVector()) in combineMul()
47888 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in combineMul()
48238 TargetLowering::DAGCombinerInfo &DCI, in combineShiftRightLogical() argument
48273 if (!DCI.isAfterLegalizeDAG()) in combineShiftRightLogical()
48458 TargetLowering::DAGCombinerInfo &DCI, in combineVectorPack() argument
48609 TargetLowering::DAGCombinerInfo &DCI, in combineVectorHADDSUB() argument
48657 TargetLowering::DAGCombinerInfo &DCI, in combineVectorShiftVar() argument
48683 if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI)) in combineVectorShiftVar()
48690 TargetLowering::DAGCombinerInfo &DCI, in combineVectorShiftImm() argument
48836 DCI)) in combineVectorShiftImm()
48843 TargetLowering::DAGCombinerInfo &DCI, in combineVectorInsert() argument
48864 APInt::getAllOnes(NumBitsPerElt), DCI)) in combineVectorInsert()
48869 if (VT.isSimple() && DCI.isAfterLegalizeDAG()) { in combineVectorInsert()
48882 TargetLowering::DAGCombinerInfo &DCI, in combineCompareEqual() argument
49204 TargetLowering::DAGCombinerInfo &DCI, in convertIntLogicToFPLogic() argument
49226 if (N0.getOpcode() == ISD::BITCAST && !DCI.isBeforeLegalizeOps()) { in convertIntLogicToFPLogic()
49711 TargetLowering::DAGCombinerInfo &DCI, in combineX86SubCmpForFlags() argument
49767 DCI.CombineTo(BrCond, NewBrCond); in combineX86SubCmpForFlags()
49772 TargetLowering::DAGCombinerInfo &DCI, in combineAndOrForCcmpCtest() argument
49852 TargetLowering::DAGCombinerInfo &DCI, in combineAnd() argument
49934 if (SDValue SetCC = combineAndOrForCcmpCtest(N, DAG, DCI, Subtarget)) in combineAnd()
49949 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, DCI, Subtarget)) in combineAnd()
49955 if (DCI.isBeforeLegalizeOps()) in combineAnd()
49958 if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget)) in combineAnd()
50055 if (TLI.SimplifyDemandedVectorElts(N0, Elts0, DCI) || in combineAnd()
50056 TLI.SimplifyDemandedVectorElts(N1, Elts1, DCI) || in combineAnd()
50057 TLI.SimplifyDemandedBits(N0, Bits0, Elts0, DCI) || in combineAnd()
50058 TLI.SimplifyDemandedBits(N1, Bits1, Elts1, DCI)) { in combineAnd()
50060 DCI.AddToWorklist(N); in combineAnd()
50298 TargetLowering::DAGCombinerInfo &DCI, in combineOrCmpEqZeroToCtlzSrl() argument
50300 if (DCI.isBeforeLegalize() || !Subtarget.getTargetLowering()->isCtlzFast()) in combineOrCmpEqZeroToCtlzSrl()
50683 TargetLowering::DAGCombinerInfo &DCI, in combineOr() argument
50722 if (SDValue SetCC = combineAndOrForCcmpCtest(N, DAG, DCI, Subtarget)) in combineOr()
50734 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, DCI, Subtarget)) in combineOr()
50737 if (DCI.isBeforeLegalizeOps()) in combineOr()
50740 if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget)) in combineOr()
50821 return TLI.SimplifyDemandedVectorElts(OtherOp, DemandedElts, DCI); in combineOr()
50825 DCI.AddToWorklist(N); in combineOr()
51139 TargetLowering::DAGCombinerInfo &DCI, in combineConstantPoolLoads() argument
51201 return DCI.CombineTo(N, Extract, SDValue(User, 1)); in combineConstantPoolLoads()
51213 TargetLowering::DAGCombinerInfo &DCI, in combineLoad() argument
51226 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() && in combineLoad()
51255 return DCI.CombineTo(N, NewVec, TF, true); in combineLoad()
51261 RegVT.getScalarType() == MVT::i1 && DCI.isBeforeLegalize()) { in combineLoad()
51270 return DCI.CombineTo(N, BoolVec, IntLoad.getValue(1), true); in combineLoad()
51292 return DCI.CombineTo(N, Extract, SDValue(User, 1)); in combineLoad()
51297 if (SDValue V = combineConstantPoolLoads(Ld, dl, DAG, DCI, Subtarget)) in combineLoad()
51386 TargetLowering::DAGCombinerInfo &DCI, in reduceMaskedLoadToScalarLoad() argument
51422 return DCI.CombineTo(ML, Insert, Load.getValue(1), true); in reduceMaskedLoadToScalarLoad()
51427 TargetLowering::DAGCombinerInfo &DCI) { in combineMaskedLoadConstantMask() argument
51447 return DCI.CombineTo(ML, Blend, VecLd.getValue(1), true); in combineMaskedLoadConstantMask()
51471 return DCI.CombineTo(ML, Blend, NewML.getValue(1), true); in combineMaskedLoadConstantMask()
51475 TargetLowering::DAGCombinerInfo &DCI, in combineMaskedLoad() argument
51485 reduceMaskedLoadToScalarLoad(Mld, DAG, DCI, Subtarget)) in combineMaskedLoad()
51490 if (SDValue Blend = combineMaskedLoadConstantMask(Mld, DAG, DCI)) in combineMaskedLoad()
51501 if (TLI.SimplifyDemandedBits(Mask, DemandedBits, DCI)) { in combineMaskedLoad()
51503 DCI.AddToWorklist(N); in combineMaskedLoad()
51554 TargetLowering::DAGCombinerInfo &DCI, in combineMaskedStore() argument
51575 if (TLI.SimplifyDemandedBits(Mask, DemandedBits, DCI)) { in combineMaskedStore()
51577 DCI.AddToWorklist(N); in combineMaskedStore()
51602 TargetLowering::DAGCombinerInfo &DCI, in combineStore() argument
51655 if (!DCI.isBeforeLegalize() && VT == MVT::v64i1 && !Subtarget.is64Bit()) { in combineStore()
51726 St->getValue().hasOneUse() && !DCI.isBeforeLegalizeOps()) { in combineStore()
51874 TargetLowering::DAGCombinerInfo &DCI, in combineVEXTRACT_STORE() argument
51887 if (TLI.SimplifyDemandedVectorElts(StoredVal, DemandedElts, DCI)) { in combineVEXTRACT_STORE()
51889 DCI.AddToWorklist(N); in combineVEXTRACT_STORE()
52663 TargetLowering::DAGCombinerInfo &DCI) { in combineVTRUNC() argument
52675 if (TLI.SimplifyDemandedBits(SDValue(N, 0), DemandedMask, DCI)) in combineVTRUNC()
52837 TargetLowering::DAGCombinerInfo &DCI, in combineFneg() argument
52865 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFneg()
53042 TargetLowering::DAGCombinerInfo &DCI, in combineXor() argument
53069 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, DCI, Subtarget)) in combineXor()
53075 if (DCI.isBeforeLegalizeOps()) in combineXor()
53128 return combineFneg(N, DAG, DCI, Subtarget); in combineXor()
53132 TargetLowering::DAGCombinerInfo &DCI, in combineBITREVERSE() argument
53142 (DCI.isBeforeLegalize() || in combineBITREVERSE()
53160 TargetLowering::DAGCombinerInfo &DCI, in combineAVG() argument
53184 TargetLowering::DAGCombinerInfo &DCI, in combineBEXTR() argument
53194 if (TLI.SimplifyDemandedBits(SDValue(N, 0), DemandedMask, DCI)) in combineBEXTR()
53285 TargetLowering::DAGCombinerInfo &DCI, in combineFOr() argument
53297 if (SDValue NewVal = combineFneg(N, DAG, DCI, Subtarget)) in combineFOr()
53392 TargetLowering::DAGCombinerInfo &DCI) { in combineX86INT_TO_FP() argument
53397 if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI)) in combineX86INT_TO_FP()
53414 DCI.CombineTo(N, Convert); in combineX86INT_TO_FP()
53416 DCI.recursivelyDeleteUnusedNodes(LN); in combineX86INT_TO_FP()
53425 TargetLowering::DAGCombinerInfo &DCI) { in combineCVTP2I_CVTTP2I() argument
53445 DCI.CombineTo(N, Convert, Convert.getValue(1)); in combineCVTP2I_CVTTP2I()
53449 DCI.CombineTo(N, Convert); in combineCVTP2I_CVTTP2I()
53452 DCI.recursivelyDeleteUnusedNodes(LN); in combineCVTP2I_CVTTP2I()
53462 TargetLowering::DAGCombinerInfo &DCI, in combineAndnp() argument
53566 if (TLI.SimplifyDemandedVectorElts(N0, Elts0, DCI) || in combineAndnp()
53567 TLI.SimplifyDemandedVectorElts(N1, Elts1, DCI) || in combineAndnp()
53568 TLI.SimplifyDemandedBits(N0, Bits0, Elts0, DCI) || in combineAndnp()
53569 TLI.SimplifyDemandedBits(N1, Bits1, Elts1, DCI)) { in combineAndnp()
53571 DCI.AddToWorklist(N); in combineAndnp()
53580 TargetLowering::DAGCombinerInfo &DCI) { in combineBT() argument
53586 if (DAG.getTargetLoweringInfo().SimplifyDemandedBits(N1, DemandedMask, DCI)) { in combineBT()
53588 DCI.AddToWorklist(N); in combineBT()
53596 TargetLowering::DAGCombinerInfo &DCI) { in combineCVTPH2PS() argument
53603 if (TLI.SimplifyDemandedVectorElts(Src, DemandedElts, DCI)) { in combineCVTPH2PS()
53605 DCI.AddToWorklist(N); in combineCVTPH2PS()
53618 DCI.CombineTo(N, Convert, Convert.getValue(1)); in combineCVTPH2PS()
53622 DCI.CombineTo(N, Convert); in combineCVTPH2PS()
53626 DCI.recursivelyDeleteUnusedNodes(LN); in combineCVTPH2PS()
53911 TargetLowering::DAGCombinerInfo &DCI, in combineSext() argument
53918 if (!DCI.isBeforeLegalizeOps() && in combineSext()
53923 DCI.CombineTo(N, Setcc); in combineSext()
53928 DCI.CombineTo(N0.getNode(), Trunc); in combineSext()
53937 if (!DCI.isBeforeLegalizeOps()) in combineSext()
53944 DAG, DCI, Subtarget)) in combineSext()
54015 TargetLowering::DAGCombinerInfo &DCI, in combineFMA() argument
54045 auto invertIfNegative = [&DAG, &TLI, &DCI](SDValue &V) { in combineFMA()
54047 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFMA()
54103 TargetLowering::DAGCombinerInfo &DCI) { in combineFMADDSUB() argument
54108 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFMADDSUB()
54126 TargetLowering::DAGCombinerInfo &DCI, in combineZext() argument
54134 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ANY_EXTEND && in combineZext()
54139 DCI.CombineTo(N, Setcc); in combineZext()
54144 DCI.CombineTo(N0.getNode(), Trunc); in combineZext()
54153 if (DCI.isBeforeLegalizeOps()) in combineZext()
54158 DAG, DCI, Subtarget)) in combineZext()
54168 if (SDValue R = combineOrCmpEqZeroToCtlzSrl(N, DAG, DCI, Subtarget)) in combineZext()
54205 TargetLowering::DAGCombinerInfo &DCI, in combineSetCC() argument
54268 isa<ConstantSDNode>(RHS) && !DCI.isBeforeLegalize()) { in combineSetCC()
54494 TargetLowering::DAGCombinerInfo &DCI, in combineMOVMSK() argument
54604 if (TLI.SimplifyDemandedBits(SDValue(N, 0), DemandedMask, DCI)) in combineMOVMSK()
54611 TargetLowering::DAGCombinerInfo &DCI, in combineTESTP() argument
54619 if (TLI.SimplifyDemandedBits(SDValue(N, 0), DemandedMask, DCI)) in combineTESTP()
54626 TargetLowering::DAGCombinerInfo &DCI) { in combineX86GatherScatter() argument
54634 if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI)) { in combineX86GatherScatter()
54636 DCI.AddToWorklist(N); in combineX86GatherScatter()
54669 TargetLowering::DAGCombinerInfo &DCI) { in combineGatherScatter() argument
54677 if (DCI.isBeforeLegalize()) { in combineGatherScatter()
54751 if (DCI.isBeforeLegalizeOps()) { in combineGatherScatter()
54767 if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI)) { in combineGatherScatter()
54769 DCI.AddToWorklist(N); in combineGatherScatter()
54966 TargetLowering::DAGCombinerInfo &DCI, in combineSIntToFP() argument
55031 if (DCI.isBeforeLegalize() || TruncVT != MVT::v2i32) { in combineSIntToFP()
55149 TargetLowering::DAGCombinerInfo &DCI, in combineCMP() argument
55165 combineX86SubCmpForFlags(N, SDValue(N, 0), DAG, DCI, Subtarget)) in combineCMP()
55296 TargetLowering::DAGCombinerInfo &DCI, in combineX86AddSub() argument
55309 if (SDValue CMP = combineX86SubCmpForFlags(N, SDValue(N, 1), DAG, DCI, ST)) in combineX86AddSub()
55326 DCI.CombineTo(GenericAddSub, Op); in combineX86AddSub()
55361 TargetLowering::DAGCombinerInfo &DCI) { in combineADC() argument
55388 return DCI.CombineTo(N, Res1, CarryOut); in combineADC()
55776 TargetLowering::DAGCombinerInfo &DCI, in combineAdd() argument
55939 TargetLowering::DAGCombinerInfo &DCI, in combineSub() argument
56077 TargetLowering::DAGCombinerInfo &DCI, in combineConcatVectorOps() argument
56741 TargetLowering::DAGCombinerInfo &DCI, in combineCONCAT_VECTORS() argument
56769 DCI, Subtarget)) in combineCONCAT_VECTORS()
56777 TargetLowering::DAGCombinerInfo &DCI, in combineINSERT_SUBVECTOR() argument
56779 if (DCI.isBeforeLegalizeOps()) in combineINSERT_SUBVECTOR()
56871 combineConcatVectorOps(dl, OpVT, SubVectorOps, DAG, DCI, Subtarget)) in combineINSERT_SUBVECTOR()
56988 TargetLowering::DAGCombinerInfo &DCI, in combineEXTRACT_SUBVECTOR() argument
57033 if (DCI.isBeforeLegalizeOps()) in combineEXTRACT_SUBVECTOR()
57285 TargetLowering::DAGCombinerInfo &DCI, in combinePMULDQ() argument
57302 if (TLI.SimplifyDemandedBits(SDValue(N, 0), APInt::getAllOnes(64), DCI)) in combinePMULDQ()
57338 TargetLowering::DAGCombinerInfo &DCI) { in combineVPMADD() argument
57376 if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI)) in combineVPMADD()
57383 TargetLowering::DAGCombinerInfo &DCI, in combineEXTEND_VECTOR_INREG() argument
57393 if (!DCI.isBeforeLegalizeOps() && ISD::isNormalLoad(In.getNode()) && in combineEXTEND_VECTOR_INREG()
57427 if (!DCI.isBeforeLegalizeOps() && Opcode == ISD::ZERO_EXTEND_VECTOR_INREG && in combineEXTEND_VECTOR_INREG()
57451 TargetLowering::DAGCombinerInfo &DCI) { in combineKSHIFT() argument
57459 if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, DCI)) in combineKSHIFT()
57491 TargetLowering::DAGCombinerInfo &DCI, in combineFP_EXTEND() argument
57500 if (DCI.isAfterLegalizeDAG() && Src.getOpcode() == ISD::FP_ROUND && in combineFP_EXTEND()
57588 TargetLowering::DAGCombinerInfo &DCI) { in combineBROADCAST_LOAD() argument
57617 return DCI.CombineTo(N, Extract, SDValue(User, 1)); in combineBROADCAST_LOAD()
57736 TargetLowering::DAGCombinerInfo &DCI) { in combinePDEP() argument
57739 if (TLI.SimplifyDemandedBits(SDValue(N, 0), APInt::getAllOnes(NumBits), DCI)) in combinePDEP()
57746 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
57747 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
57756 return combineExtractVectorElt(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57758 return combineCONCAT_VECTORS(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57760 return combineINSERT_SUBVECTOR(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57762 return combineEXTRACT_SUBVECTOR(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57765 case X86ISD::BLENDV: return combineSelect(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57766 case ISD::BITCAST: return combineBitcast(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57767 case X86ISD::CMOV: return combineCMov(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57768 case X86ISD::CMP: return combineCMP(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57769 case ISD::ADD: return combineAdd(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57770 case ISD::SUB: return combineSub(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57772 case X86ISD::SUB: return combineX86AddSub(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57776 case X86ISD::ADC: return combineADC(N, DAG, DCI); in PerformDAGCombine()
57777 case ISD::MUL: return combineMul(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57780 case ISD::SRL: return combineShiftRightLogical(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57781 case ISD::AND: return combineAnd(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57782 case ISD::OR: return combineOr(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57783 case ISD::XOR: return combineXor(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57784 case ISD::BITREVERSE: return combineBITREVERSE(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57788 case ISD::AVGFLOORU: return combineAVG(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57790 case X86ISD::BEXTRI: return combineBEXTR(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57791 case ISD::LOAD: return combineLoad(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57792 case ISD::MLOAD: return combineMaskedLoad(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57793 case ISD::STORE: return combineStore(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57794 case ISD::MSTORE: return combineMaskedStore(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57796 return combineVEXTRACT_STORE(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57799 return combineSIntToFP(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57809 case ISD::FNEG: return combineFneg(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57811 case X86ISD::VTRUNC: return combineVTRUNC(N, DAG, DCI); in PerformDAGCombine()
57812 case X86ISD::ANDNP: return combineAndnp(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57816 case X86ISD::FOR: return combineFOr(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57822 case X86ISD::CVTUI2P: return combineX86INT_TO_FP(N, DAG, DCI); in PerformDAGCombine()
57829 return combineCVTP2I_CVTTP2I(N, DAG, DCI); in PerformDAGCombine()
57831 case X86ISD::CVTPH2PS: return combineCVTPH2PS(N, DAG, DCI); in PerformDAGCombine()
57832 case X86ISD::BT: return combineBT(N, DAG, DCI); in PerformDAGCombine()
57834 case ISD::ZERO_EXTEND: return combineZext(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57835 case ISD::SIGN_EXTEND: return combineSext(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57840 return combineEXTEND_VECTOR_INREG(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57841 case ISD::SETCC: return combineSetCC(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57845 case X86ISD::PACKUS: return combineVectorPack(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57849 case X86ISD::FHSUB: return combineVectorHADDSUB(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57853 return combineVectorShiftVar(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57857 return combineVectorShiftImm(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57860 case X86ISD::PINSRW: return combineVectorInsert(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57895 case ISD::VECTOR_SHUFFLE: return combineShuffle(N, DAG, DCI,Subtarget); in PerformDAGCombine()
57907 case ISD::STRICT_FMA: return combineFMA(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57911 case X86ISD::FMSUBADD: return combineFMADDSUB(N, DAG, DCI); in PerformDAGCombine()
57912 case X86ISD::MOVMSK: return combineMOVMSK(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57913 case X86ISD::TESTP: return combineTESTP(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57915 case X86ISD::MSCATTER: return combineX86GatherScatter(N, DAG, DCI); in PerformDAGCombine()
57917 case ISD::MSCATTER: return combineGatherScatter(N, DAG, DCI); in PerformDAGCombine()
57921 case X86ISD::PMULUDQ: return combinePMULDQ(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57923 case X86ISD::VPMADDWD: return combineVPMADD(N, DAG, DCI); in PerformDAGCombine()
57925 case X86ISD::KSHIFTR: return combineKSHIFT(N, DAG, DCI); in PerformDAGCombine()
57928 case ISD::FP_EXTEND: return combineFP_EXTEND(N, DAG, DCI, Subtarget); in PerformDAGCombine()
57932 case X86ISD::SUBV_BROADCAST_LOAD: return combineBROADCAST_LOAD(N, DAG, DCI); in PerformDAGCombine()
57934 case X86ISD::PDEP: return combinePDEP(N, DAG, DCI); in PerformDAGCombine()