Lines Matching refs:Amt
4658 SDValue Amt = DAG.getTargetConstant(EltSizeInBits, dl, MVT::i8); in getPack() local
4661 LHS = DAG.getNode(X86ISD::VSRLI, dl, OpVT, LHS, Amt); in getPack()
4662 RHS = DAG.getNode(X86ISD::VSRLI, dl, OpVT, RHS, Amt); in getPack()
4672 LHS = DAG.getNode(X86ISD::VSHLI, dl, OpVT, LHS, Amt); in getPack()
4673 RHS = DAG.getNode(X86ISD::VSHLI, dl, OpVT, RHS, Amt); in getPack()
4675 LHS = DAG.getNode(X86ISD::VSRAI, dl, OpVT, LHS, Amt); in getPack()
4676 RHS = DAG.getNode(X86ISD::VSRAI, dl, OpVT, RHS, Amt); in getPack()
6866 uint64_t Amt = AmtC->getZExtValue(); in findEltLoadSrc() local
6867 if ((Amt % 8) == 0 && findEltLoadSrc(Elt.getOperand(0), Ld, ByteOffset)) { in findEltLoadSrc()
6868 ByteOffset += Amt / 8; in findEltLoadSrc()
25223 SDValue Amt = DAG.getConstant(ShiftAmt, dl, VT); in getTargetVShiftByConstNode() local
25224 if (SDValue C = DAG.FoldConstantArithmetic(ShiftOpc, dl, VT, {SrcOp, Amt})) in getTargetVShiftByConstNode()
29082 uint64_t getGFNICtrlImm(unsigned Opcode, unsigned Amt = 0) { in getGFNICtrlImm() argument
29083 assert((Amt < 8) && "Shift/Rotation amount out of range"); in getGFNICtrlImm()
29088 return ((0x0102040810204080ULL >> (Amt)) & in getGFNICtrlImm()
29089 (0x0101010101010101ULL * (0xFF >> (Amt)))); in getGFNICtrlImm()
29091 return ((0x0102040810204080ULL << (Amt)) & in getGFNICtrlImm()
29092 (0x0101010101010101ULL * ((0xFF << (Amt)) & 0xFF))); in getGFNICtrlImm()
29094 return (getGFNICtrlImm(ISD::SRL, Amt) | in getGFNICtrlImm()
29095 (0x8080808080808080ULL >> (64 - (8 * Amt)))); in getGFNICtrlImm()
29097 return getGFNICtrlImm(ISD::SRL, 8 - Amt) | getGFNICtrlImm(ISD::SHL, Amt); in getGFNICtrlImm()
29099 return getGFNICtrlImm(ISD::SHL, 8 - Amt) | getGFNICtrlImm(ISD::SRL, Amt); in getGFNICtrlImm()
29106 unsigned Amt = 0) { in getGFNICtrlMask() argument
29109 uint64_t Imm = getGFNICtrlImm(Opcode, Amt); in getGFNICtrlMask()
29188 SDValue Amt = Op.getOperand(1); in LowerShiftByScalarImmediate() local
29233 if (!X86::isConstantSplat(Amt, APIntShiftAmt)) in LowerShiftByScalarImmediate()
29270 Mask = DAG.getNode(Op.getOpcode(), dl, VT, Mask, Amt); in LowerShiftByScalarImmediate()
29331 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt); in LowerShiftByScalarImmediate()
29349 SDValue Amt = Op.getOperand(1); in LowerShiftByScalarVariable() local
29354 if (SDValue BaseShAmt = DAG.getSplatSourceVector(Amt, BaseShAmtIdx)) { in LowerShiftByScalarVariable()
29408 static SDValue convertShiftLeftToScale(SDValue Amt, const SDLoc &dl, in convertShiftLeftToScale() argument
29411 MVT VT = Amt.getSimpleValueType(); in convertShiftLeftToScale()
29426 if (getTargetConstantBitsFromNode(Amt, SVTBits, UndefElts, EltBits)) { in convertShiftLeftToScale()
29441 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT)); in convertShiftLeftToScale()
29442 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, in convertShiftLeftToScale()
29444 Amt = DAG.getBitcast(MVT::v4f32, Amt); in convertShiftLeftToScale()
29445 return DAG.getNode(ISD::FP_TO_SINT, dl, VT, Amt); in convertShiftLeftToScale()
29451 SDValue Lo = DAG.getBitcast(MVT::v4i32, getUnpackl(DAG, dl, VT, Amt, Z)); in convertShiftLeftToScale()
29452 SDValue Hi = DAG.getBitcast(MVT::v4i32, getUnpackh(DAG, dl, VT, Amt, Z)); in convertShiftLeftToScale()
29468 SDValue Amt = Op.getOperand(1); in LowerShift() local
29470 bool ConstantAmt = ISD::isBuildVectorOfConstantSDNodes(Amt.getNode()); in LowerShift()
29495 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt); in LowerShift()
29496 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt); in LowerShift()
29507 Amt = DAG.getNegative(Amt, dl, VT); in LowerShift()
29509 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt); in LowerShift()
29511 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt); in LowerShift()
29518 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0}); in LowerShift()
29519 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1}); in LowerShift()
29541 SDValue A = Amt->getOperand(i); in LowerShift()
29583 if (SDValue Scale = convertShiftLeftToScale(Amt, dl, Subtarget, DAG)) in LowerShift()
29591 SDValue RAmt = DAG.getNode(ISD::SUB, dl, VT, EltBits, Amt); in LowerShift()
29594 SDValue ZAmt = DAG.getSetCC(dl, VT, Amt, Zero, ISD::SETEQ); in LowerShift()
29608 DAG.isKnownNeverZero(Amt))) { in LowerShift()
29610 SDValue RAmt = DAG.getNode(ISD::SUB, dl, VT, EltBits, Amt); in LowerShift()
29613 DAG.getSetCC(dl, VT, Amt, DAG.getConstant(0, dl, VT), ISD::SETEQ); in LowerShift()
29615 DAG.getSetCC(dl, VT, Amt, DAG.getConstant(1, dl, VT), ISD::SETEQ); in LowerShift()
29632 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0}); in LowerShift()
29633 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1}); in LowerShift()
29634 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2}); in LowerShift()
29635 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3}); in LowerShift()
29643 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1}); in LowerShift()
29644 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1}); in LowerShift()
29645 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1}); in LowerShift()
29646 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1}); in LowerShift()
29648 SDValue Amt01 = DAG.getBitcast(MVT::v8i16, Amt); in LowerShift()
29693 Amt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Amt); in LowerShift()
29695 DAG.getNode(Opc, dl, ExtVT, R, Amt)); in LowerShift()
29710 Amt = DAG.getZExtOrTrunc(Amt, dl, ExVT); in LowerShift()
29711 Amt = DAG.getNode(ISD::SUB, dl, ExVT, DAG.getConstant(8, dl, ExVT), Amt); in LowerShift()
29712 Amt = DAG.getNode(ISD::SHL, dl, ExVT, DAG.getConstant(1, dl, ExVT), Amt); in LowerShift()
29713 assert(ISD::isBuildVectorOfConstantSDNodes(Amt.getNode()) && in LowerShift()
29719 R = DAG.getNode(ISD::MUL, dl, ExVT, R, Amt); in LowerShift()
29727 LoAmt.push_back(Amt.getOperand(i + j)); in LowerShift()
29728 HiAmt.push_back(Amt.getOperand(i + j + 8)); in LowerShift()
29784 Amt = DAG.getBitcast(ExtVT, Amt); in LowerShift()
29785 Amt = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ExtVT, Amt, 5, DAG); in LowerShift()
29786 Amt = DAG.getBitcast(VT, Amt); in LowerShift()
29791 R = SignBitSelect(VT, Amt, M, R); in LowerShift()
29794 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt); in LowerShift()
29798 R = SignBitSelect(VT, Amt, M, R); in LowerShift()
29801 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt); in LowerShift()
29805 R = SignBitSelect(VT, Amt, M, R); in LowerShift()
29813 SDValue ALo = getUnpackl(DAG, dl, VT, DAG.getUNDEF(VT), Amt); in LowerShift()
29814 SDValue AHi = getUnpackh(DAG, dl, VT, DAG.getUNDEF(VT), Amt); in LowerShift()
29859 SDValue ALo = getUnpackl(DAG, dl, VT, Amt, Z); in LowerShift()
29860 SDValue AHi = getUnpackh(DAG, dl, VT, Amt, Z); in LowerShift()
29878 !ISD::isBuildVectorOfConstantSDNodes(Amt.getNode()); in LowerShift()
29903 Amt = DAG.getNode( in LowerShift()
29905 getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Amt, 4, DAG), in LowerShift()
29906 getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Amt, 12, DAG)); in LowerShift()
29908 Amt = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Amt, 12, DAG); in LowerShift()
29913 R = SignBitSelect(Amt, M, R); in LowerShift()
29916 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt); in LowerShift()
29920 R = SignBitSelect(Amt, M, R); in LowerShift()
29923 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt); in LowerShift()
29927 R = SignBitSelect(Amt, M, R); in LowerShift()
29930 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt); in LowerShift()
29934 R = SignBitSelect(Amt, M, R); in LowerShift()
29957 SDValue Amt = Op.getOperand(2); in LowerFunnelShift() local
29963 bool IsCstSplat = X86::isConstantSplat(Amt, APIntShiftAmt); in LowerFunnelShift()
29977 {Op0, Op1, Amt}, DAG, Subtarget); in LowerFunnelShift()
30026 SDValue AmtMod = DAG.getNode(ISD::AND, DL, VT, Amt, AmtMask); in LowerFunnelShift()
30119 !isa<ConstantSDNode>(Amt)) { in LowerFunnelShift()
30120 SDValue Mask = DAG.getConstant(EltSizeInBits - 1, DL, Amt.getValueType()); in LowerFunnelShift()
30121 SDValue HiShift = DAG.getConstant(EltSizeInBits, DL, Amt.getValueType()); in LowerFunnelShift()
30124 Amt = DAG.getNode(ISD::AND, DL, Amt.getValueType(), Amt, Mask); in LowerFunnelShift()
30128 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, Res, Amt); in LowerFunnelShift()
30130 Res = DAG.getNode(ISD::SHL, DL, MVT::i32, Res, Amt); in LowerFunnelShift()
30141 Amt = DAG.getNode(ISD::AND, DL, Amt.getValueType(), Amt, in LowerFunnelShift()
30142 DAG.getConstant(15, DL, Amt.getValueType())); in LowerFunnelShift()
30144 return DAG.getNode(FSHOp, DL, VT, Op0, Op1, Amt); in LowerFunnelShift()
30157 SDValue Amt = Op.getOperand(1); in LowerRotate() local
30165 bool IsCstSplat = X86::isConstantSplat(Amt, CstSplatValue); in LowerRotate()
30190 return DAG.getNode(FunnelOpc, DL, VT, R, R, Amt); in LowerRotate()
30198 if (SDValue NegAmt = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {Z, Amt})) in LowerRotate()
30204 DAG.getNode(ISD::SUB, DL, VT, Z, Amt)); in LowerRotate()
30267 SDValue AmtMod = DAG.getNode(ISD::AND, DL, VT, Amt, AmtMask); in LowerRotate()
30277 return DAG.getNode(FunnelOpc, DL, VT, R, R, Amt); in LowerRotate()
30290 bool ConstantAmt = ISD::isBuildVectorOfConstantSDNodes(Amt.getNode()); in LowerRotate()
30329 Amt = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT, AmtMod); in LowerRotate()
30330 R = DAG.getNode(ShiftOpc, DL, WideVT, R, Amt); in LowerRotate()
30357 Amt = DAG.getNode(ISD::SUB, DL, VT, Z, Amt); in LowerRotate()
30367 Amt = DAG.getBitcast(ExtVT, Amt); in LowerRotate()
30368 Amt = DAG.getNode(ISD::SHL, DL, ExtVT, Amt, DAG.getConstant(5, DL, ExtVT)); in LowerRotate()
30369 Amt = DAG.getBitcast(VT, Amt); in LowerRotate()
30377 R = SignBitSelect(VT, Amt, M, R); in LowerRotate()
30380 Amt = DAG.getNode(ISD::ADD, DL, VT, Amt, Amt); in LowerRotate()
30387 R = SignBitSelect(VT, Amt, M, R); in LowerRotate()
30390 Amt = DAG.getNode(ISD::ADD, DL, VT, Amt, Amt); in LowerRotate()
30397 return SignBitSelect(VT, Amt, M, R); in LowerRotate()
30400 bool IsSplatAmt = DAG.isSplatValue(Amt); in LowerRotate()
30407 Amt = DAG.getNode(ISD::AND, DL, VT, Amt, AmtMask); in LowerRotate()
30409 AmtR = DAG.getNode(ISD::SUB, DL, VT, AmtR, Amt); in LowerRotate()
30410 SDValue SHL = DAG.getNode(IsROTL ? ISD::SHL : ISD::SRL, DL, VT, R, Amt); in LowerRotate()
30417 Amt = DAG.getNode(ISD::SUB, DL, VT, Z, Amt); in LowerRotate()
30422 Amt = DAG.getNode(ISD::AND, DL, VT, Amt, AmtMask); in LowerRotate()
30428 SDValue Scale = convertShiftLeftToScale(Amt, DL, Subtarget, DAG); in LowerRotate()
41964 SDValue Amt = Op.getOperand(1); in SimplifyDemandedVectorEltsForTargetNode() local
41965 MVT AmtVT = Amt.getSimpleValueType(); in SimplifyDemandedVectorEltsForTargetNode()
41970 bool AssumeSingleUse = llvm::all_of(Amt->uses(), [&Amt](SDNode *Use) { in SimplifyDemandedVectorEltsForTargetNode()
41974 Use->getOperand(0) != Amt; in SimplifyDemandedVectorEltsForTargetNode()
41980 if (SimplifyDemandedVectorElts(Amt, AmtElts, AmtUndef, AmtZero, TLO, in SimplifyDemandedVectorEltsForTargetNode()
42048 auto *Amt = cast<ConstantSDNode>(Op.getOperand(1)); in SimplifyDemandedVectorEltsForTargetNode() local
42049 assert(Amt->getAPIntValue().ult(NumElts) && "Out of range shift amount"); in SimplifyDemandedVectorEltsForTargetNode()
42050 unsigned ShiftAmt = Amt->getZExtValue(); in SimplifyDemandedVectorEltsForTargetNode()
42087 auto *Amt = cast<ConstantSDNode>(Op.getOperand(1)); in SimplifyDemandedVectorEltsForTargetNode() local
42088 assert(Amt->getAPIntValue().ult(NumElts) && "Out of range shift amount"); in SimplifyDemandedVectorEltsForTargetNode()
42089 unsigned ShiftAmt = Amt->getZExtValue(); in SimplifyDemandedVectorEltsForTargetNode()
43843 if (auto *Amt = dyn_cast<ConstantSDNode>(V.getOperand(1))) in combineBitcastToBoolVector() local
43848 DAG.getTargetConstant(Amt->getZExtValue(), DL, MVT::i8)); in combineBitcastToBoolVector()