2687   return ISD::isBitwiseLogicOp(Opcode) || X86ISD::ANDNP == Opcode;  in isLogicOp()
2745   case X86ISD::ANDNP:  in isTargetShuffleVariableMask()
4542   RHS = DAG.getNode(X86ISD::ANDNP, DL, VT, Mask, RHS);  in getBitSelect()
5837   case X86ISD::ANDNP: {  in getFauxShuffleMask()
5843     bool IsAndN = (X86ISD::ANDNP == Opcode);  in getFauxShuffleMask()
28507         SDValue BHi = DAG.getNode(X86ISD::ANDNP, dl, VT, Mask, B);  in LowerMUL()
33714   NODE_NAME_CASE(ANDNP)  in getTargetNodeName()
34153   case X86ISD::ANDNP:  in isBinOp()
37043         (Opcode == ISD::OR || Opcode == ISD::XOR || Opcode == X86ISD::ANDNP) &&  in targetShrinkDemandedConstant()
37327   case X86ISD::ANDNP: {  in computeKnownBitsForTargetNode()
37732   case X86ISD::ANDNP: {  in ComputeNumSignBitsForTargetNode()
42124   case X86ISD::ANDNP: {  in SimplifyDemandedVectorEltsForTargetNode()
42717   case X86ISD::ANDNP: {  in SimplifyDemandedBitsForTargetNode()
43220   case X86ISD::ANDNP: {  in SimplifyMultipleUseDemandedBitsForTargetNode()
43398   case X86ISD::ANDNP: return X86ISD::FANDN;  in getAltBitOpcode()
45552       AndN = DAG.getNode(X86ISD::ANDNP, DL, CondVT, Cond, CastRHS);  in combineVSelectWithAllOnesOrZeros()
46905       if (BC.getOpcode() == X86ISD::ANDNP || BC.getOpcode() == X86ISD::FANDN) {  in combinePTESTCC()
49010   return DAG.getNode(X86ISD::ANDNP, SDLoc(N), VT, X, Y);  in combineAndNotIntoANDNP()
49085     SDValue LoV = DAG.getNode(X86ISD::ANDNP, DL, SplitVT, {LoX, LoY});  in combineAndShuffleNot()
49086     SDValue HiV = DAG.getNode(X86ISD::ANDNP, DL, SplitVT, {HiX, HiY});  in combineAndShuffleNot()
49091     return DAG.getNode(X86ISD::ANDNP, DL, VT, {X, Y});  in combineAndShuffleNot()
49422       return DAG.getNode(X86ISD::ANDNP, DL, VT, Sra, Y);  in combineAndMaskToShift()
50176       DAG.getNode(X86ISD::ANDNP, DL, VT, DAG.getBitcast(VT, N0.getOperand(1)),  in canonicalizeBitSelect()
50194   if (N0.getOpcode() != ISD::AND || N1.getOpcode() != X86ISD::ANDNP)  in matchLogicBlend()
52962   case X86ISD::FANDN: IntOpcode = X86ISD::ANDNP; break;  in lowerX86FPLogicOp()
56465     case X86ISD::ANDNP:  in combineConcatVectorOps()
57812   case X86ISD::ANDNP:       return combineAndnp(N, DAG, DCI, Subtarget);  in PerformDAGCombine()