Lines Matching refs:vvvv
871 insn->vvvv = in fixupReg()
872 (Reg)fixupRegValue(insn, (OperandType)op->type, insn->vvvv, &valid); in fixupReg()
1587 int vvvv; in readVVVV() local
1589 vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 | in readVVVV()
1592 vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]); in readVVVV()
1594 vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]); in readVVVV()
1596 vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]); in readVVVV()
1601 vvvv &= 0xf; // Can only clear bit 4. Bit 3 must be cleared later. in readVVVV()
1603 insn->vvvv = static_cast<Reg>(vvvv); in readVVVV()
1632 needVVVV = hasVVVV && (insn->vvvv != 0); in readOperands()
1643 needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0); in readOperands()
1777 insn->vvvv = static_cast<Reg>(insn->vvvv & 0x7); in readOperands()
2419 translateRegister(mcInst, insn.vvvv); in translateOperand()