Lines Matching refs:insn
190 static bool peek(struct InternalInstruction *insn, uint8_t &byte) { in peek() argument
191 uint64_t offset = insn->readerCursor - insn->startLocation; in peek()
192 if (offset >= insn->bytes.size()) in peek()
194 byte = insn->bytes[offset]; in peek()
198 template <typename T> static bool consume(InternalInstruction *insn, T &ptr) { in consume() argument
199 auto r = insn->bytes; in consume()
200 uint64_t offset = insn->readerCursor - insn->startLocation; in consume()
204 insn->readerCursor += sizeof(T); in consume()
208 static bool isREX(struct InternalInstruction *insn, uint8_t prefix) { in isREX() argument
209 return insn->mode == MODE_64BIT && prefix >= 0x40 && prefix <= 0x4f; in isREX()
212 static bool isREX2(struct InternalInstruction *insn, uint8_t prefix) { in isREX2() argument
213 return insn->mode == MODE_64BIT && prefix == 0xd5; in isREX2()
221 static int readPrefixes(struct InternalInstruction *insn) { in readPrefixes() argument
231 if (consume(insn, byte)) in readPrefixes()
236 if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0) // LOCK in readPrefixes()
239 if ((byte == 0xf2 || byte == 0xf3) && !peek(insn, nextByte)) { in readPrefixes()
247 insn->xAcquireRelease = true; in readPrefixes()
257 insn->xAcquireRelease = true; in readPrefixes()
260 if (isREX(insn, nextByte)) { in readPrefixes()
263 if (consume(insn, nnextByte)) in readPrefixes()
266 if (peek(insn, nnextByte)) in readPrefixes()
268 --insn->readerCursor; in readPrefixes()
274 insn->hasLockPrefix = true; in readPrefixes()
279 if (peek(insn, nextByte)) in readPrefixes()
289 if (isREX(insn, nextByte) || isREX2(insn, nextByte) || nextByte == 0x0f || in readPrefixes()
292 insn->mandatoryPrefix = byte; in readPrefixes()
293 insn->repeatPrefix = byte; in readPrefixes()
297 insn->segmentOverride = SEG_OVERRIDE_CS; in readPrefixes()
300 insn->segmentOverride = SEG_OVERRIDE_SS; in readPrefixes()
303 insn->segmentOverride = SEG_OVERRIDE_DS; in readPrefixes()
306 insn->segmentOverride = SEG_OVERRIDE_ES; in readPrefixes()
309 insn->segmentOverride = SEG_OVERRIDE_FS; in readPrefixes()
312 insn->segmentOverride = SEG_OVERRIDE_GS; in readPrefixes()
316 insn->hasOpSize = true; in readPrefixes()
317 if (peek(insn, nextByte)) in readPrefixes()
320 if (!insn->mandatoryPrefix && (nextByte == 0x0f || isREX(insn, nextByte))) in readPrefixes()
321 insn->mandatoryPrefix = byte; in readPrefixes()
325 insn->hasAdSize = true; in readPrefixes()
336 insn->vectorExtensionType = TYPE_NO_VEX_XOP; in readPrefixes()
340 if (consume(insn, byte1)) { in readPrefixes()
345 if (peek(insn, byte2)) { in readPrefixes()
350 if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)) { in readPrefixes()
351 insn->vectorExtensionType = TYPE_EVEX; in readPrefixes()
353 --insn->readerCursor; // unconsume byte1 in readPrefixes()
354 --insn->readerCursor; // unconsume byte in readPrefixes()
357 if (insn->vectorExtensionType == TYPE_EVEX) { in readPrefixes()
358 insn->vectorExtensionPrefix[0] = byte; in readPrefixes()
359 insn->vectorExtensionPrefix[1] = byte1; in readPrefixes()
360 if (consume(insn, insn->vectorExtensionPrefix[2])) { in readPrefixes()
364 if (consume(insn, insn->vectorExtensionPrefix[3])) { in readPrefixes()
369 if (insn->mode == MODE_64BIT) { in readPrefixes()
371 insn->rexPrefix = 0x40 | in readPrefixes()
372 (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3) | in readPrefixes()
373 (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2) | in readPrefixes()
374 (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1) | in readPrefixes()
375 (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0); in readPrefixes()
378 insn->rex2ExtensionPrefix[1] = in readPrefixes()
379 (r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 6) | in readPrefixes()
380 (x2FromEVEX3of4(insn->vectorExtensionPrefix[2]) << 5) | in readPrefixes()
381 (b2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4); in readPrefixes()
387 insn->vectorExtensionPrefix[0], insn->vectorExtensionPrefix[1], in readPrefixes()
388 insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3])); in readPrefixes()
392 if (peek(insn, byte1)) { in readPrefixes()
397 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) in readPrefixes()
398 insn->vectorExtensionType = TYPE_VEX_3B; in readPrefixes()
400 --insn->readerCursor; in readPrefixes()
402 if (insn->vectorExtensionType == TYPE_VEX_3B) { in readPrefixes()
403 insn->vectorExtensionPrefix[0] = byte; in readPrefixes()
404 consume(insn, insn->vectorExtensionPrefix[1]); in readPrefixes()
405 consume(insn, insn->vectorExtensionPrefix[2]); in readPrefixes()
409 if (insn->mode == MODE_64BIT) in readPrefixes()
410 insn->rexPrefix = 0x40 | in readPrefixes()
411 (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3) | in readPrefixes()
412 (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2) | in readPrefixes()
413 (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1) | in readPrefixes()
414 (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0); in readPrefixes()
417 insn->vectorExtensionPrefix[0], in readPrefixes()
418 insn->vectorExtensionPrefix[1], in readPrefixes()
419 insn->vectorExtensionPrefix[2])); in readPrefixes()
423 if (peek(insn, byte1)) { in readPrefixes()
428 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) in readPrefixes()
429 insn->vectorExtensionType = TYPE_VEX_2B; in readPrefixes()
431 --insn->readerCursor; in readPrefixes()
433 if (insn->vectorExtensionType == TYPE_VEX_2B) { in readPrefixes()
434 insn->vectorExtensionPrefix[0] = byte; in readPrefixes()
435 consume(insn, insn->vectorExtensionPrefix[1]); in readPrefixes()
437 if (insn->mode == MODE_64BIT) in readPrefixes()
438 insn->rexPrefix = in readPrefixes()
439 0x40 | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2); in readPrefixes()
441 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) { in readPrefixes()
445 insn->hasOpSize = true; in readPrefixes()
450 insn->vectorExtensionPrefix[0], in readPrefixes()
451 insn->vectorExtensionPrefix[1])); in readPrefixes()
455 if (peek(insn, byte1)) { in readPrefixes()
461 insn->vectorExtensionType = TYPE_XOP; in readPrefixes()
463 --insn->readerCursor; in readPrefixes()
465 if (insn->vectorExtensionType == TYPE_XOP) { in readPrefixes()
466 insn->vectorExtensionPrefix[0] = byte; in readPrefixes()
467 consume(insn, insn->vectorExtensionPrefix[1]); in readPrefixes()
468 consume(insn, insn->vectorExtensionPrefix[2]); in readPrefixes()
472 if (insn->mode == MODE_64BIT) in readPrefixes()
473 insn->rexPrefix = 0x40 | in readPrefixes()
474 (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3) | in readPrefixes()
475 (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2) | in readPrefixes()
476 (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1) | in readPrefixes()
477 (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0); in readPrefixes()
479 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) { in readPrefixes()
483 insn->hasOpSize = true; in readPrefixes()
488 insn->vectorExtensionPrefix[0], in readPrefixes()
489 insn->vectorExtensionPrefix[1], in readPrefixes()
490 insn->vectorExtensionPrefix[2])); in readPrefixes()
492 } else if (isREX2(insn, byte)) { in readPrefixes()
494 if (peek(insn, byte1)) { in readPrefixes()
498 insn->rex2ExtensionPrefix[0] = byte; in readPrefixes()
499 consume(insn, insn->rex2ExtensionPrefix[1]); in readPrefixes()
502 insn->rexPrefix = 0x40 | (wFromREX2(insn->rex2ExtensionPrefix[1]) << 3) | in readPrefixes()
503 (rFromREX2(insn->rex2ExtensionPrefix[1]) << 2) | in readPrefixes()
504 (xFromREX2(insn->rex2ExtensionPrefix[1]) << 1) | in readPrefixes()
505 (bFromREX2(insn->rex2ExtensionPrefix[1]) << 0); in readPrefixes()
507 insn->rex2ExtensionPrefix[0], in readPrefixes()
508 insn->rex2ExtensionPrefix[1])); in readPrefixes()
509 } else if (isREX(insn, byte)) { in readPrefixes()
510 if (peek(insn, nextByte)) in readPrefixes()
512 insn->rexPrefix = byte; in readPrefixes()
515 --insn->readerCursor; in readPrefixes()
517 if (insn->mode == MODE_16BIT) { in readPrefixes()
518 insn->registerSize = (insn->hasOpSize ? 4 : 2); in readPrefixes()
519 insn->addressSize = (insn->hasAdSize ? 4 : 2); in readPrefixes()
520 insn->displacementSize = (insn->hasAdSize ? 4 : 2); in readPrefixes()
521 insn->immediateSize = (insn->hasOpSize ? 4 : 2); in readPrefixes()
522 } else if (insn->mode == MODE_32BIT) { in readPrefixes()
523 insn->registerSize = (insn->hasOpSize ? 2 : 4); in readPrefixes()
524 insn->addressSize = (insn->hasAdSize ? 2 : 4); in readPrefixes()
525 insn->displacementSize = (insn->hasAdSize ? 2 : 4); in readPrefixes()
526 insn->immediateSize = (insn->hasOpSize ? 2 : 4); in readPrefixes()
527 } else if (insn->mode == MODE_64BIT) { in readPrefixes()
528 insn->displacementSize = 4; in readPrefixes()
529 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) { in readPrefixes()
530 insn->registerSize = 8; in readPrefixes()
531 insn->addressSize = (insn->hasAdSize ? 4 : 8); in readPrefixes()
532 insn->immediateSize = 4; in readPrefixes()
533 insn->hasOpSize = false; in readPrefixes()
535 insn->registerSize = (insn->hasOpSize ? 2 : 4); in readPrefixes()
536 insn->addressSize = (insn->hasAdSize ? 4 : 8); in readPrefixes()
537 insn->immediateSize = (insn->hasOpSize ? 2 : 4); in readPrefixes()
545 static int readSIB(struct InternalInstruction *insn) { in readSIB() argument
550 switch (insn->addressSize) { in readSIB()
555 insn->sibIndexBase = SIB_INDEX_EAX; in readSIB()
559 insn->sibIndexBase = SIB_INDEX_RAX; in readSIB()
564 if (consume(insn, insn->sib)) in readSIB()
567 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3) | in readSIB()
568 (x2FromREX2(insn->rex2ExtensionPrefix[1]) << 4); in readSIB()
571 insn->sibIndex = SIB_INDEX_NONE; in readSIB()
573 insn->sibIndex = (SIBIndex)(insn->sibIndexBase + index); in readSIB()
576 insn->sibScale = 1 << scaleFromSIB(insn->sib); in readSIB()
578 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3) | in readSIB()
579 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4); in readSIB()
584 switch (modFromModRM(insn->modRM)) { in readSIB()
586 insn->eaDisplacement = EA_DISP_32; in readSIB()
587 insn->sibBase = SIB_BASE_NONE; in readSIB()
590 insn->eaDisplacement = EA_DISP_8; in readSIB()
591 insn->sibBase = (SIBBase)(sibBaseBase + base); in readSIB()
594 insn->eaDisplacement = EA_DISP_32; in readSIB()
595 insn->sibBase = (SIBBase)(sibBaseBase + base); in readSIB()
602 insn->sibBase = (SIBBase)(sibBaseBase + base); in readSIB()
609 static int readDisplacement(struct InternalInstruction *insn) { in readDisplacement() argument
615 insn->displacementOffset = insn->readerCursor - insn->startLocation; in readDisplacement()
616 switch (insn->eaDisplacement) { in readDisplacement()
620 if (consume(insn, d8)) in readDisplacement()
622 insn->displacement = d8; in readDisplacement()
625 if (consume(insn, d16)) in readDisplacement()
627 insn->displacement = d16; in readDisplacement()
630 if (consume(insn, d32)) in readDisplacement()
632 insn->displacement = d32; in readDisplacement()
640 static int readModRM(struct InternalInstruction *insn) { in readModRM() argument
644 if (insn->consumedModRM) in readModRM()
647 if (consume(insn, insn->modRM)) in readModRM()
649 insn->consumedModRM = true; in readModRM()
651 mod = modFromModRM(insn->modRM); in readModRM()
652 rm = rmFromModRM(insn->modRM); in readModRM()
653 reg = regFromModRM(insn->modRM); in readModRM()
658 switch (insn->registerSize) { in readModRM()
660 insn->regBase = MODRM_REG_AX; in readModRM()
661 insn->eaRegBase = EA_REG_AX; in readModRM()
664 insn->regBase = MODRM_REG_EAX; in readModRM()
665 insn->eaRegBase = EA_REG_EAX; in readModRM()
668 insn->regBase = MODRM_REG_RAX; in readModRM()
669 insn->eaRegBase = EA_REG_RAX; in readModRM()
673 reg |= (rFromREX(insn->rexPrefix) << 3) | in readModRM()
674 (r2FromREX2(insn->rex2ExtensionPrefix[1]) << 4); in readModRM()
675 rm |= (bFromREX(insn->rexPrefix) << 3) | in readModRM()
676 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4); in readModRM()
678 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT) in readModRM()
679 reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4; in readModRM()
681 insn->reg = (Reg)(insn->regBase + reg); in readModRM()
683 switch (insn->addressSize) { in readModRM()
690 insn->eaBase = EA_BASE_NONE; in readModRM()
691 insn->eaDisplacement = EA_DISP_16; in readModRM()
692 if (readDisplacement(insn)) in readModRM()
695 insn->eaBase = (EABase)(eaBaseBase + rm); in readModRM()
696 insn->eaDisplacement = EA_DISP_NONE; in readModRM()
700 insn->eaBase = (EABase)(eaBaseBase + rm); in readModRM()
701 insn->eaDisplacement = EA_DISP_8; in readModRM()
702 insn->displacementSize = 1; in readModRM()
703 if (readDisplacement(insn)) in readModRM()
707 insn->eaBase = (EABase)(eaBaseBase + rm); in readModRM()
708 insn->eaDisplacement = EA_DISP_16; in readModRM()
709 if (readDisplacement(insn)) in readModRM()
713 insn->eaBase = (EABase)(insn->eaRegBase + rm); in readModRM()
714 if (readDisplacement(insn)) in readModRM()
722 EABase eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX); in readModRM()
726 insn->eaDisplacement = EA_DISP_NONE; // readSIB may override this in readModRM()
732 insn->eaBase = (insn->addressSize == 4 ? EA_BASE_sib : EA_BASE_sib64); in readModRM()
733 if (readSIB(insn) || readDisplacement(insn)) in readModRM()
737 insn->eaBase = EA_BASE_NONE; in readModRM()
738 insn->eaDisplacement = EA_DISP_32; in readModRM()
739 if (readDisplacement(insn)) in readModRM()
743 insn->eaBase = (EABase)(eaBaseBase + rm); in readModRM()
748 insn->displacementSize = 1; in readModRM()
751 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32); in readModRM()
754 insn->eaBase = EA_BASE_sib; in readModRM()
755 if (readSIB(insn) || readDisplacement(insn)) in readModRM()
759 insn->eaBase = (EABase)(eaBaseBase + rm); in readModRM()
760 if (readDisplacement(insn)) in readModRM()
766 insn->eaDisplacement = EA_DISP_NONE; in readModRM()
767 insn->eaBase = (EABase)(insn->eaRegBase + rm); in readModRM()
778 static uint16_t name(struct InternalInstruction *insn, OperandType type, \
789 if (insn->rexPrefix && index >= 4 && index <= 7) \
851 GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
852 GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
861 static int fixupReg(struct InternalInstruction *insn, in fixupReg() argument
871 insn->vvvv = in fixupReg()
872 (Reg)fixupRegValue(insn, (OperandType)op->type, insn->vvvv, &valid); in fixupReg()
877 insn->reg = (Reg)fixupRegValue(insn, (OperandType)op->type, in fixupReg()
878 insn->reg - insn->regBase, &valid); in fixupReg()
883 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT && in fixupReg()
884 modFromModRM(insn->modRM) == 3) { in fixupReg()
899 insn->eaBase = in fixupReg()
900 (EABase)(insn->eaBase + in fixupReg()
901 (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4)); in fixupReg()
907 if (insn->eaBase >= insn->eaRegBase) { in fixupReg()
908 insn->eaBase = (EABase)fixupRMValue( in fixupReg()
909 insn, (OperandType)op->type, insn->eaBase - insn->eaRegBase, &valid); in fixupReg()
921 static bool readOpcode(struct InternalInstruction *insn) { in readOpcode() argument
925 insn->opcodeType = ONEBYTE; in readOpcode()
926 if (insn->vectorExtensionType == TYPE_EVEX) { in readOpcode()
927 switch (mmmFromEVEX2of4(insn->vectorExtensionPrefix[1])) { in readOpcode()
931 mmmFromEVEX2of4(insn->vectorExtensionPrefix[1]))); in readOpcode()
934 insn->opcodeType = TWOBYTE; in readOpcode()
935 return consume(insn, insn->opcode); in readOpcode()
937 insn->opcodeType = THREEBYTE_38; in readOpcode()
938 return consume(insn, insn->opcode); in readOpcode()
940 insn->opcodeType = THREEBYTE_3A; in readOpcode()
941 return consume(insn, insn->opcode); in readOpcode()
943 insn->opcodeType = MAP4; in readOpcode()
944 return consume(insn, insn->opcode); in readOpcode()
946 insn->opcodeType = MAP5; in readOpcode()
947 return consume(insn, insn->opcode); in readOpcode()
949 insn->opcodeType = MAP6; in readOpcode()
950 return consume(insn, insn->opcode); in readOpcode()
952 insn->opcodeType = MAP7; in readOpcode()
953 return consume(insn, insn->opcode); in readOpcode()
955 } else if (insn->vectorExtensionType == TYPE_VEX_3B) { in readOpcode()
956 switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) { in readOpcode()
960 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]))); in readOpcode()
963 insn->opcodeType = TWOBYTE; in readOpcode()
964 return consume(insn, insn->opcode); in readOpcode()
966 insn->opcodeType = THREEBYTE_38; in readOpcode()
967 return consume(insn, insn->opcode); in readOpcode()
969 insn->opcodeType = THREEBYTE_3A; in readOpcode()
970 return consume(insn, insn->opcode); in readOpcode()
972 insn->opcodeType = MAP5; in readOpcode()
973 return consume(insn, insn->opcode); in readOpcode()
975 insn->opcodeType = MAP6; in readOpcode()
976 return consume(insn, insn->opcode); in readOpcode()
978 insn->opcodeType = MAP7; in readOpcode()
979 return consume(insn, insn->opcode); in readOpcode()
981 } else if (insn->vectorExtensionType == TYPE_VEX_2B) { in readOpcode()
982 insn->opcodeType = TWOBYTE; in readOpcode()
983 return consume(insn, insn->opcode); in readOpcode()
984 } else if (insn->vectorExtensionType == TYPE_XOP) { in readOpcode()
985 switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) { in readOpcode()
989 mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1]))); in readOpcode()
992 insn->opcodeType = XOP8_MAP; in readOpcode()
993 return consume(insn, insn->opcode); in readOpcode()
995 insn->opcodeType = XOP9_MAP; in readOpcode()
996 return consume(insn, insn->opcode); in readOpcode()
998 insn->opcodeType = XOPA_MAP; in readOpcode()
999 return consume(insn, insn->opcode); in readOpcode()
1001 } else if (mFromREX2(insn->rex2ExtensionPrefix[1])) { in readOpcode()
1003 insn->opcodeType = TWOBYTE; in readOpcode()
1004 return consume(insn, insn->opcode); in readOpcode()
1007 if (consume(insn, current)) in readOpcode()
1013 if (consume(insn, current)) in readOpcode()
1019 if (consume(insn, current)) in readOpcode()
1022 insn->opcodeType = THREEBYTE_38; in readOpcode()
1026 if (consume(insn, current)) in readOpcode()
1029 insn->opcodeType = THREEBYTE_3A; in readOpcode()
1035 if (readModRM(insn)) in readOpcode()
1038 if (consume(insn, current)) in readOpcode()
1041 insn->opcodeType = THREEDNOW_MAP; in readOpcode()
1044 insn->opcodeType = TWOBYTE; in readOpcode()
1046 } else if (insn->mandatoryPrefix) in readOpcode()
1049 insn->mandatoryPrefix = 0; in readOpcode()
1053 insn->opcode = current; in readOpcode()
1090 struct InternalInstruction *insn, in getInstructionIDWithAttrMask() argument
1094 switch (insn->opcodeType) { in getInstructionIDWithAttrMask()
1134 .modRMDecisions[insn->opcode] in getInstructionIDWithAttrMask()
1136 if (readModRM(insn)) in getInstructionIDWithAttrMask()
1139 decode(insn->opcodeType, insnCtx, insn->opcode, insn->modRM); in getInstructionIDWithAttrMask()
1141 *instructionID = decode(insn->opcodeType, insnCtx, insn->opcode, 0); in getInstructionIDWithAttrMask()
1147 static bool isCCMPOrCTEST(InternalInstruction *insn) { in isCCMPOrCTEST() argument
1148 if (insn->opcodeType != MAP4) in isCCMPOrCTEST()
1150 if (insn->opcode == 0x83 && regFromModRM(insn->modRM) == 7) in isCCMPOrCTEST()
1152 switch (insn->opcode & 0xfe) { in isCCMPOrCTEST()
1160 return regFromModRM(insn->modRM) == 7; in isCCMPOrCTEST()
1162 return regFromModRM(insn->modRM) == 0; in isCCMPOrCTEST()
1166 static bool isNF(InternalInstruction *insn) { in isNF() argument
1167 if (!nfFromEVEX4of4(insn->vectorExtensionPrefix[3])) in isNF()
1169 if (insn->opcodeType == MAP4) in isNF()
1172 if (insn->opcodeType == THREEBYTE_38 && in isNF()
1173 ppFromEVEX3of4(insn->vectorExtensionPrefix[2]) == VEX_PREFIX_NONE) { in isNF()
1174 switch (insn->opcode) { in isNF()
1190 static int getInstructionID(struct InternalInstruction *insn, in getInstructionID() argument
1199 if (insn->mode == MODE_64BIT) in getInstructionID()
1202 if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) { in getInstructionID()
1203 attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX; in getInstructionID()
1205 if (insn->vectorExtensionType == TYPE_EVEX) { in getInstructionID()
1206 switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) { in getInstructionID()
1218 if (zFromEVEX4of4(insn->vectorExtensionPrefix[3])) in getInstructionID()
1220 if (bFromEVEX4of4(insn->vectorExtensionPrefix[3])) in getInstructionID()
1222 if (isNF(insn) && !readModRM(insn) && in getInstructionID()
1223 !isCCMPOrCTEST(insn)) // NF bit is the MSB of aaa. in getInstructionID()
1226 else if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]) && in getInstructionID()
1227 (insn->opcodeType != MAP4)) in getInstructionID()
1229 if (lFromEVEX4of4(insn->vectorExtensionPrefix[3])) in getInstructionID()
1231 if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3])) in getInstructionID()
1233 } else if (insn->vectorExtensionType == TYPE_VEX_3B) { in getInstructionID()
1234 switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) { in getInstructionID()
1246 if (lFromVEX3of3(insn->vectorExtensionPrefix[2])) in getInstructionID()
1248 } else if (insn->vectorExtensionType == TYPE_VEX_2B) { in getInstructionID()
1249 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) { in getInstructionID()
1252 if (insn->hasAdSize) in getInstructionID()
1263 if (lFromVEX2of2(insn->vectorExtensionPrefix[1])) in getInstructionID()
1265 } else if (insn->vectorExtensionType == TYPE_XOP) { in getInstructionID()
1266 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) { in getInstructionID()
1278 if (lFromXOP3of3(insn->vectorExtensionPrefix[2])) in getInstructionID()
1283 } else if (!insn->mandatoryPrefix) { in getInstructionID()
1285 if (insn->hasOpSize && (insn->mode != MODE_16BIT)) in getInstructionID()
1287 if (insn->hasAdSize) in getInstructionID()
1289 if (insn->opcodeType == ONEBYTE) { in getInstructionID()
1290 if (insn->repeatPrefix == 0xf3 && (insn->opcode == 0x90)) in getInstructionID()
1294 if (insn->repeatPrefix == 0xf2) in getInstructionID()
1296 else if (insn->repeatPrefix == 0xf3) in getInstructionID()
1300 switch (insn->mandatoryPrefix) { in getInstructionID()
1308 if (insn->mode != MODE_16BIT) in getInstructionID()
1310 if (insn->hasAdSize) in getInstructionID()
1319 if (insn->rexPrefix & 0x08) { in getInstructionID()
1325 if (insn->rex2ExtensionPrefix[0] == 0xd5 && insn->opcodeType == ONEBYTE && in getInstructionID()
1326 (insn->opcode == 0xA1 || (insn->opcode & 0xf0) == 0x50)) in getInstructionID()
1329 if (insn->mode == MODE_16BIT) { in getInstructionID()
1332 if (insn->opcodeType == ONEBYTE && insn->opcode == 0xE3) in getInstructionID()
1337 if (!insn->hasOpSize && insn->opcodeType == ONEBYTE && in getInstructionID()
1338 (insn->opcode == 0xE8 || insn->opcode == 0xE9)) in getInstructionID()
1341 if (!insn->hasOpSize && insn->opcodeType == TWOBYTE && in getInstructionID()
1342 insn->opcode >= 0x80 && insn->opcode <= 0x8F) in getInstructionID()
1347 if (getInstructionIDWithAttrMask(&instructionID, insn, attrMask)) in getInstructionID()
1352 if (insn->mode != MODE_64BIT && in getInstructionID()
1353 insn->vectorExtensionType != TYPE_NO_VEX_XOP) { in getInstructionID()
1356 if ((insn->vectorExtensionType == TYPE_EVEX && in getInstructionID()
1357 wFromEVEX3of4(insn->vectorExtensionPrefix[2])) || in getInstructionID()
1358 (insn->vectorExtensionType == TYPE_VEX_3B && in getInstructionID()
1359 wFromVEX3of3(insn->vectorExtensionPrefix[2])) || in getInstructionID()
1360 (insn->vectorExtensionType == TYPE_XOP && in getInstructionID()
1361 wFromXOP3of3(insn->vectorExtensionPrefix[2]))) { in getInstructionID()
1364 if (getInstructionIDWithAttrMask(&instructionIDWithREXW, insn, in getInstructionID()
1366 insn->instructionID = instructionID; in getInstructionID()
1367 insn->spec = &INSTRUCTIONS_SYM[instructionID]; in getInstructionID()
1374 insn->instructionID = instructionIDWithREXW; in getInstructionID()
1375 insn->spec = &INSTRUCTIONS_SYM[instructionIDWithREXW]; in getInstructionID()
1386 if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) || in getInstructionID()
1387 (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) || in getInstructionID()
1388 (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8) || in getInstructionID()
1389 (insn->opcodeType == MAP4 && insn->opcode == 0xF8)) { in getInstructionID()
1391 if (insn->hasAdSize) in getInstructionID()
1393 if (insn->hasOpSize) in getInstructionID()
1397 if (insn->mode == MODE_16BIT) { in getInstructionID()
1401 if (insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) in getInstructionID()
1405 if (getInstructionIDWithAttrMask(&instructionID, insn, attrMask)) in getInstructionID()
1408 insn->instructionID = instructionID; in getInstructionID()
1409 insn->spec = &INSTRUCTIONS_SYM[instructionID]; in getInstructionID()
1413 if ((insn->mode == MODE_16BIT || insn->hasOpSize) && in getInstructionID()
1426 if (getInstructionIDWithAttrMask(&instructionIDWithOpsize, insn, in getInstructionID()
1430 insn->instructionID = instructionID; in getInstructionID()
1431 insn->spec = spec; in getInstructionID()
1439 (insn->mode == MODE_16BIT) ^ insn->hasOpSize) { in getInstructionID()
1440 insn->instructionID = instructionIDWithOpsize; in getInstructionID()
1441 insn->spec = &INSTRUCTIONS_SYM[instructionIDWithOpsize]; in getInstructionID()
1443 insn->instructionID = instructionID; in getInstructionID()
1444 insn->spec = spec; in getInstructionID()
1449 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 && in getInstructionID()
1450 insn->rexPrefix & 0x01) { in getInstructionID()
1460 insn->opcode = 0x91; in getInstructionID()
1462 if (getInstructionIDWithAttrMask(&instructionIDWithNewOpcode, insn, in getInstructionID()
1464 insn->opcode = 0x90; in getInstructionID()
1466 insn->instructionID = instructionID; in getInstructionID()
1467 insn->spec = spec; in getInstructionID()
1474 insn->opcode = 0x90; in getInstructionID()
1476 insn->instructionID = instructionIDWithNewOpcode; in getInstructionID()
1477 insn->spec = specWithNewOpcode; in getInstructionID()
1482 insn->instructionID = instructionID; in getInstructionID()
1483 insn->spec = &INSTRUCTIONS_SYM[insn->instructionID]; in getInstructionID()
1496 static int readOpcodeRegister(struct InternalInstruction *insn, uint8_t size) { in readOpcodeRegister() argument
1500 size = insn->registerSize; in readOpcodeRegister()
1503 insn->opcodeRegister = in readOpcodeRegister()
1504 (Reg)(base + ((bFromREX(insn->rexPrefix) << 3) | in readOpcodeRegister()
1505 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4) | in readOpcodeRegister()
1506 (insn->opcode & 7))); in readOpcodeRegister()
1512 if (insn->rexPrefix && insn->opcodeRegister >= MODRM_REG_AL + 0x4 && in readOpcodeRegister()
1513 insn->opcodeRegister < MODRM_REG_AL + 0x8) { in readOpcodeRegister()
1514 insn->opcodeRegister = in readOpcodeRegister()
1515 (Reg)(MODRM_REG_SPL + (insn->opcodeRegister - MODRM_REG_AL - 4)); in readOpcodeRegister()
1540 static int readImmediate(struct InternalInstruction *insn, uint8_t size) { in readImmediate() argument
1548 assert(insn->numImmediatesConsumed < 2 && "Already consumed two immediates"); in readImmediate()
1550 insn->immediateSize = size; in readImmediate()
1551 insn->immediateOffset = insn->readerCursor - insn->startLocation; in readImmediate()
1555 if (consume(insn, imm8)) in readImmediate()
1557 insn->immediates[insn->numImmediatesConsumed] = imm8; in readImmediate()
1560 if (consume(insn, imm16)) in readImmediate()
1562 insn->immediates[insn->numImmediatesConsumed] = imm16; in readImmediate()
1565 if (consume(insn, imm32)) in readImmediate()
1567 insn->immediates[insn->numImmediatesConsumed] = imm32; in readImmediate()
1570 if (consume(insn, imm64)) in readImmediate()
1572 insn->immediates[insn->numImmediatesConsumed] = imm64; in readImmediate()
1578 insn->numImmediatesConsumed++; in readImmediate()
1584 static int readVVVV(struct InternalInstruction *insn) { in readVVVV() argument
1588 if (insn->vectorExtensionType == TYPE_EVEX) in readVVVV()
1589 vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 | in readVVVV()
1590 vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2])); in readVVVV()
1591 else if (insn->vectorExtensionType == TYPE_VEX_3B) in readVVVV()
1592 vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]); in readVVVV()
1593 else if (insn->vectorExtensionType == TYPE_VEX_2B) in readVVVV()
1594 vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]); in readVVVV()
1595 else if (insn->vectorExtensionType == TYPE_XOP) in readVVVV()
1596 vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]); in readVVVV()
1600 if (insn->mode != MODE_64BIT) in readVVVV()
1603 insn->vvvv = static_cast<Reg>(vvvv); in readVVVV()
1611 static int readMaskRegister(struct InternalInstruction *insn) { in readMaskRegister() argument
1614 if (insn->vectorExtensionType != TYPE_EVEX) in readMaskRegister()
1617 insn->writemask = in readMaskRegister()
1618 static_cast<Reg>(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3])); in readMaskRegister()
1624 static int readOperands(struct InternalInstruction *insn) { in readOperands() argument
1631 hasVVVV = !readVVVV(insn); in readOperands()
1632 needVVVV = hasVVVV && (insn->vvvv != 0); in readOperands()
1634 for (const auto &Op : x86OperandSets[insn->spec->operands]) { in readOperands()
1643 needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0); in readOperands()
1644 if (readModRM(insn)) in readOperands()
1648 if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64) in readOperands()
1652 if (insn->sibIndex == SIB_INDEX_NONE) in readOperands()
1653 insn->sibIndex = (SIBIndex)(insn->sibIndexBase + 4); in readOperands()
1656 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT && in readOperands()
1657 v2FromEVEX4of4(insn->vectorExtensionPrefix[3])) in readOperands()
1658 insn->sibIndex = (SIBIndex)(insn->sibIndex + 16); in readOperands()
1666 insn->sibIndex = in readOperands()
1667 (SIBIndex)(SIB_INDEX_XMM0 + (insn->sibIndex - insn->sibIndexBase)); in readOperands()
1670 insn->sibIndex = in readOperands()
1671 (SIBIndex)(SIB_INDEX_YMM0 + (insn->sibIndex - insn->sibIndexBase)); in readOperands()
1674 insn->sibIndex = in readOperands()
1675 (SIBIndex)(SIB_INDEX_ZMM0 + (insn->sibIndex - insn->sibIndexBase)); in readOperands()
1680 if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) in readOperands()
1681 insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB); in readOperands()
1685 if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64) in readOperands()
1687 if (readModRM(insn)) in readOperands()
1689 if (fixupReg(insn, &Op)) in readOperands()
1694 if (readModRM(insn)) in readOperands()
1696 if (fixupReg(insn, &Op)) in readOperands()
1699 if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) in readOperands()
1700 insn->displacement *= 1 << (Op.encoding - ENCODING_RM); in readOperands()
1706 insn->immediates[insn->numImmediatesConsumed] = in readOperands()
1707 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf; in readOperands()
1708 ++insn->numImmediatesConsumed; in readOperands()
1711 if (readImmediate(insn, 1)) in readOperands()
1717 if (readImmediate(insn, 2)) in readOperands()
1721 if (readImmediate(insn, 4)) in readOperands()
1725 if (readImmediate(insn, 8)) in readOperands()
1729 if (readImmediate(insn, insn->immediateSize)) in readOperands()
1733 if (readImmediate(insn, insn->addressSize)) in readOperands()
1737 insn->RC = (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 1) | in readOperands()
1738 lFromEVEX4of4(insn->vectorExtensionPrefix[3]); in readOperands()
1741 if (readOpcodeRegister(insn, 1)) in readOperands()
1745 if (readOpcodeRegister(insn, 2)) in readOperands()
1749 if (readOpcodeRegister(insn, 4)) in readOperands()
1753 if (readOpcodeRegister(insn, 8)) in readOperands()
1757 if (readOpcodeRegister(insn, 0)) in readOperands()
1761 insn->immediates[1] = oszcFromEVEX3of4(insn->vectorExtensionPrefix[2]); in readOperands()
1765 if (isCCMPOrCTEST(insn)) in readOperands()
1766 insn->immediates[2] = scFromEVEX4of4(insn->vectorExtensionPrefix[3]); in readOperands()
1768 insn->immediates[1] = insn->opcode & 0xf; in readOperands()
1776 if (insn->mode != MODE_64BIT) in readOperands()
1777 insn->vvvv = static_cast<Reg>(insn->vvvv & 0x7); in readOperands()
1778 if (fixupReg(insn, &Op)) in readOperands()
1782 if (readMaskRegister(insn)) in readOperands()
1942 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) { in translateSrcIndex() argument
1945 if (insn.mode == MODE_64BIT) in translateSrcIndex()
1946 baseRegNo = insn.hasAdSize ? X86::ESI : X86::RSI; in translateSrcIndex()
1947 else if (insn.mode == MODE_32BIT) in translateSrcIndex()
1948 baseRegNo = insn.hasAdSize ? X86::SI : X86::ESI; in translateSrcIndex()
1950 assert(insn.mode == MODE_16BIT); in translateSrcIndex()
1951 baseRegNo = insn.hasAdSize ? X86::ESI : X86::SI; in translateSrcIndex()
1957 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateSrcIndex()
1967 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) { in translateDstIndex() argument
1970 if (insn.mode == MODE_64BIT) in translateDstIndex()
1971 baseRegNo = insn.hasAdSize ? X86::EDI : X86::RDI; in translateDstIndex()
1972 else if (insn.mode == MODE_32BIT) in translateDstIndex()
1973 baseRegNo = insn.hasAdSize ? X86::DI : X86::EDI; in translateDstIndex()
1975 assert(insn.mode == MODE_16BIT); in translateDstIndex()
1976 baseRegNo = insn.hasAdSize ? X86::EDI : X86::DI; in translateDstIndex()
1991 InternalInstruction &insn, in translateImmediate() argument
2001 pcrel = insn.startLocation + insn.length; in translateImmediate()
2006 switch (insn.displacementSize) { in translateImmediate()
2077 mcInst, immediate + pcrel, insn.startLocation, isBranch, in translateImmediate()
2078 insn.immediateOffset, insn.immediateSize, insn.length)) in translateImmediate()
2083 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateImmediate()
2095 InternalInstruction &insn) { in translateRMRegister() argument
2096 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { in translateRMRegister()
2101 switch (insn.eaBase) { in translateRMRegister()
2133 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, in translateRMMemory() argument
2155 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) { in translateRMMemory()
2156 if (insn.sibBase != SIB_BASE_NONE) { in translateRMMemory()
2157 switch (insn.sibBase) { in translateRMMemory()
2171 if (insn.sibIndex != SIB_INDEX_NONE) { in translateRMMemory()
2172 switch (insn.sibIndex) { in translateRMMemory()
2195 (insn.sibScale != 1 || in translateRMMemory()
2196 (insn.sibBase == SIB_BASE_NONE && insn.mode != MODE_64BIT) || in translateRMMemory()
2197 (insn.sibBase != SIB_BASE_NONE && in translateRMMemory()
2198 insn.sibBase != SIB_BASE_ESP && insn.sibBase != SIB_BASE_RSP && in translateRMMemory()
2199 insn.sibBase != SIB_BASE_R12D && insn.sibBase != SIB_BASE_R12))) { in translateRMMemory()
2200 indexReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIZ : in translateRMMemory()
2206 scaleAmount = MCOperand::createImm(insn.sibScale); in translateRMMemory()
2208 switch (insn.eaBase) { in translateRMMemory()
2210 if (insn.eaDisplacement == EA_DISP_NONE) { in translateRMMemory()
2214 if (insn.mode == MODE_64BIT){ in translateRMMemory()
2215 pcrel = insn.startLocation + insn.length; in translateRMMemory()
2216 Dis->tryAddingPcLoadReferenceComment(insn.displacement + pcrel, in translateRMMemory()
2217 insn.startLocation + in translateRMMemory()
2218 insn.displacementOffset); in translateRMMemory()
2220 baseReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIP : in translateRMMemory()
2246 switch (insn.eaBase) { in translateRMMemory()
2271 displacement = MCOperand::createImm(insn.displacement); in translateRMMemory()
2273 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateRMMemory()
2280 (insn.eaDisplacement == EA_DISP_NONE) ? 0 : insn.displacementSize; in translateRMMemory()
2283 mcInst, insn.displacement + pcrel, insn.startLocation, false, in translateRMMemory()
2284 insn.displacementOffset, dispSize, insn.length)) in translateRMMemory()
2299 InternalInstruction &insn, const MCDisassembler *Dis) { in translateRM() argument
2319 return translateRMRegister(mcInst, insn); in translateRM()
2324 return translateRMMemory(mcInst, insn, Dis); in translateRM()
2326 return translateRMMemory(mcInst, insn, Dis, true); in translateRM()
2365 InternalInstruction &insn, in translateOperand() argument
2372 translateRegister(mcInst, insn.reg); in translateOperand()
2375 return translateMaskRegister(mcInst, insn.writemask); in translateOperand()
2379 return translateRM(mcInst, operand, insn, Dis); in translateOperand()
2387 insn.immediates[insn.numImmediatesTranslated++], in translateOperand()
2389 insn, in translateOperand()
2393 mcInst.addOperand(MCOperand::createImm(insn.RC)); in translateOperand()
2396 return translateSrcIndex(mcInst, insn); in translateOperand()
2398 return translateDstIndex(mcInst, insn); in translateOperand()
2404 translateRegister(mcInst, insn.opcodeRegister); in translateOperand()
2407 mcInst.addOperand(MCOperand::createImm(insn.immediates[1])); in translateOperand()
2410 if (isCCMPOrCTEST(&insn)) in translateOperand()
2411 mcInst.addOperand(MCOperand::createImm(insn.immediates[2])); in translateOperand()
2413 mcInst.addOperand(MCOperand::createImm(insn.immediates[1])); in translateOperand()
2416 translateFPRegister(mcInst, insn.modRM & 7); in translateOperand()
2419 translateRegister(mcInst, insn.vvvv); in translateOperand()
2422 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0], in translateOperand()
2423 insn, Dis); in translateOperand()
2434 InternalInstruction &insn, in translateInstruction() argument
2436 if (!insn.spec) { in translateInstruction()
2442 mcInst.setOpcode(insn.instructionID); in translateInstruction()
2446 if (insn.xAcquireRelease) { in translateInstruction()
2453 insn.numImmediatesTranslated = 0; in translateInstruction()
2455 for (const auto &Op : insn.operands) { in translateInstruction()
2457 if (translateOperand(mcInst, Op, insn, Dis)) { in translateInstruction()