Lines Matching full:vec
68 class Vec {
78 Vec split;
81 def I8x16 : Vec {
93 def I16x8 : Vec {
106 def I32x4 : Vec {
119 def I64x2 : Vec {
132 def F32x4 : Vec {
144 def F64x2 : Vec {
156 def F16x8 : Vec {
191 foreach vec = AllVecs in {
192 defm : LoadPat<vec.vt, load, "LOAD_V128">;
220 foreach vec = AllVecs in {
221 defvar inst = "LOAD"#vec.lane_bits#"_SPLAT";
222 defm : LoadPat<vec.vt,
223 PatFrag<(ops node:$addr), (splat_vector (vec.lane_vt (vec.lane_load node:$addr)))>,
228 multiclass SIMDLoadExtend<Vec vec, string loadPat, bits<32> simdop> {
229 defvar signed = vec.prefix#".load"#loadPat#"_s";
230 defvar unsigned = vec.prefix#".load"#loadPat#"_u";
232 defm LOAD_EXTEND_S_#vec#_A32 :
238 defm LOAD_EXTEND_U_#vec#_A32 :
244 defm LOAD_EXTEND_S_#vec#_A64 :
250 defm LOAD_EXTEND_U_#vec#_A64 :
263 foreach vec = [I16x8, I32x4, I64x2] in
267 defvar loadpat = !cast<PatFrag>(exts[0]#vec.split.lane_bits);
268 defvar inst = "LOAD_EXTEND"#exts[1]#"_"#vec;
269 defm : LoadPat<vec.vt, loadpat, inst>;
273 multiclass SIMDLoadZero<Vec vec, bits<32> simdop> {
274 defvar name = "v128.load"#vec.lane_bits#"_zero";
276 defm LOAD_ZERO_#vec#_A32 :
282 defm LOAD_ZERO_#vec#_A64 :
296 foreach vec = [I32x4, I64x2] in {
297 defvar inst = "LOAD_ZERO_"#vec;
298 defvar pat = PatFrag<(ops node:$addr), (scalar_to_vector (vec.lane_vt (load $addr)))>;
299 defm : LoadPat<vec.vt, pat, inst>;
303 foreach vec = [I32x4, I64x2] in {
304 defvar inst = "LOAD_ZERO_"#vec;
306 (vector_insert (vec.splat (vec.lane_vt 0)), (vec.lane_vt (load $ptr)), 0)>;
307 defm : LoadPat<vec.vt, pat, inst>;
311 multiclass SIMDLoadLane<Vec vec, bits<32> simdop> {
312 defvar name = "v128.load"#vec.lane_bits#"_lane";
314 defm LOAD_LANE_#vec#_A32 :
317 I32:$addr, V128:$vec),
319 [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx",
321 defm LOAD_LANE_#vec#_A64 :
324 I64:$addr, V128:$vec),
326 [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx",
337 multiclass LoadLanePatNoOffset<Vec vec, SDPatternOperator kind> {
338 defvar load_lane_a32 = !cast<NI>("LOAD_LANE_"#vec#"_A32");
339 defvar load_lane_a64 = !cast<NI>("LOAD_LANE_"#vec#"_A64");
340 def : Pat<(vec.vt (kind (i32 I32:$addr),
341 (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
342 (load_lane_a32 0, 0, imm:$idx, $addr, $vec)>,
344 def : Pat<(vec.vt (kind (i64 I64:$addr),
345 (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
346 (load_lane_a64 0, 0, imm:$idx, $addr, $vec)>,
351 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
352 (vector_insert $vec, (i32 (extloadi8 $ptr)), $idx)>;
354 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
355 (vector_insert $vec, (i32 (extloadi16 $ptr)), $idx)>;
357 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
358 (vector_insert $vec, (i32 (load $ptr)), $idx)>;
360 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
361 (vector_insert $vec, (i64 (load $ptr)), $idx)>;
375 SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec),
377 "v128.store\t${off}(${addr})$p2align, $vec",
380 SIMD_I<(outs), (ins P2Align:$p2align, offset64_op:$off, I64:$addr, V128:$vec),
382 "v128.store\t${off}(${addr})$p2align, $vec",
387 foreach vec = AllVecs in {
388 defm : StorePat<vec.vt, store, "STORE_V128">;
392 multiclass SIMDStoreLane<Vec vec, bits<32> simdop> {
393 defvar name = "v128.store"#vec.lane_bits#"_lane";
395 defm STORE_LANE_#vec#_A32 :
398 I32:$addr, V128:$vec),
400 [], name#"\t${off}(${addr})$p2align, $vec, $idx",
402 defm STORE_LANE_#vec#_A64 :
405 I64:$addr, V128:$vec),
407 [], name#"\t${off}(${addr})$p2align, $vec, $idx",
417 multiclass StoreLanePat<Vec vec, SDPatternOperator kind> {
419 (vec.vt V128:$vec),
420 (i32 vec.lane_idx:$idx)),
421 (!cast<NI>("STORE_LANE_"#vec#"_A32") 0, $offset, imm:$idx, $addr, $vec)>,
424 (vec.vt V128:$vec),
425 (i32 vec.lane_idx:$idx)),
426 (!cast<NI>("STORE_LANE_"#vec#"_A64") 0, $offset, imm:$idx, $addr, $vec)>,
431 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
432 (truncstorei8 (i32 (vector_extract $vec, $idx)), $ptr)>;
434 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
435 (truncstorei16 (i32 (vector_extract $vec, $idx)), $ptr)>;
437 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
438 (store (i32 (vector_extract $vec, $idx)), $ptr)>;
440 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
441 (store (i64 (vector_extract $vec, $idx)), $ptr)>;
456 multiclass ConstVec<Vec vec, dag ops, dag pat, string args> {
458 defm CONST_V128_#vec : SIMD_I<(outs V128:$dst), ops, (outs), ops,
459 [(set V128:$dst, (vec.vt pat))],
511 foreach vec = AllVecs in {
512 defvar numEls = !div(vec.vt.Size, vec.lane_bits);
513 defvar isFloat = !or(!eq(vec.lane_vt, f32), !eq(vec.lane_vt, f64));
515 def : Pat<(vec.splat (vec.lane_vt immKind:$x)),
516 !dag(!cast<NI>("CONST_V128_"#vec),
517 !listsplat((vec.lane_vt immKind:$x), numEls),
555 foreach vec = AllVecs in {
557 def : Pat<(vec.vt (wasm_shuffle (vec.vt V128:$x), (vec.vt V128:$y),
572 def : Pat<(vec.vt (wasm_shuffle (vec.vt V128:$x), (vec.vt V128:$y),
600 multiclass Splat<Vec vec, bits<32> simdop> {
601 defm SPLAT_#vec : SIMD_I<(outs V128:$dst), (ins vec.lane_rc:$x),
603 [(set (vec.vt V128:$dst),
604 (vec.splat vec.lane_rc:$x))],
605 vec.prefix#".splat\t$dst, $x", vec.prefix#".splat",
625 foreach vec = AllVecs in
626 def : Pat<(vec.vt (scalar_to_vector (vec.lane_vt vec.lane_rc:$x))),
627 (!cast<Instruction>("SPLAT_"#vec) $x)>;
634 multiclass ExtractLane<Vec vec, bits<32> simdop, string suffix = ""> {
635 defm EXTRACT_LANE_#vec#suffix :
636 SIMD_I<(outs vec.lane_rc:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
638 vec.prefix#".extract_lane"#suffix#"\t$dst, $vec, $idx",
639 vec.prefix#".extract_lane"#suffix#"\t$idx", simdop>;
651 def : Pat<(vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)),
652 (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>;
653 def : Pat<(vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)),
654 (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>;
655 def : Pat<(vector_extract (v4i32 V128:$vec), (i32 LaneIdx4:$idx)),
656 (EXTRACT_LANE_I32x4 $vec, imm:$idx)>;
657 def : Pat<(vector_extract (v4f32 V128:$vec), (i32 LaneIdx4:$idx)),
658 (EXTRACT_LANE_F32x4 $vec, imm:$idx)>;
659 def : Pat<(vector_extract (v2i64 V128:$vec), (i32 LaneIdx2:$idx)),
660 (EXTRACT_LANE_I64x2 $vec, imm:$idx)>;
661 def : Pat<(vector_extract (v2f64 V128:$vec), (i32 LaneIdx2:$idx)),
662 (EXTRACT_LANE_F64x2 $vec, imm:$idx)>;
665 (sext_inreg (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), i8),
666 (EXTRACT_LANE_I8x16_s $vec, imm:$idx)>;
668 (and (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), (i32 0xff)),
669 (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>;
671 (sext_inreg (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), i16),
672 (EXTRACT_LANE_I16x8_s $vec, imm:$idx)>;
674 (and (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), (i32 0xffff)),
675 (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>;
678 HALF_PRECISION_I<(outs F32:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
681 (v8f16 V128:$vec), (i32 LaneIdx16:$idx)))],
682 "f16x8.extract_lane\t$dst, $vec, $idx",
686 multiclass ReplaceLane<Vec vec, bits<32> simdop> {
687 defm REPLACE_LANE_#vec :
688 SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, vec.lane_rc:$x),
691 (vec.vt V128:$vec),
692 (vec.lane_vt vec.lane_rc:$x),
693 (i32 vec.lane_idx:$idx)))],
694 vec.prefix#".replace_lane\t$dst, $vec, $idx, $x",
695 vec.prefix#".replace_lane\t$idx", simdop>;
706 def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef),
707 (REPLACE_LANE_I8x16 $vec, 0, $x)>;
708 def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef),
709 (REPLACE_LANE_I16x8 $vec, 0, $x)>;
710 def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef),
711 (REPLACE_LANE_I32x4 $vec, 0, $x)>;
712 def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef),
713 (REPLACE_LANE_I64x2 $vec, 0, $x)>;
714 def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef),
715 (REPLACE_LANE_F32x4 $vec, 0, $x)>;
716 def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef),
717 (REPLACE_LANE_F64x2 $vec, 0, $x)>;
723 multiclass SIMDCondition<Vec vec, string name, CondCode cond, bits<32> simdop,
725 defm _#vec :
727 [(set (vec.int_vt V128:$dst),
728 (setcc (vec.vt V128:$lhs), (vec.vt V128:$rhs), cond))],
729 vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
730 vec.prefix#"."#name, simdop, reqs>;
733 multiclass HalfPrecisionCondition<Vec vec, string name, CondCode cond,
735 defm "" : SIMDCondition<vec, name, cond, simdop, [HasHalfPrecision]>;
805 multiclass SIMDBinary<Vec vec, SDPatternOperator node, string name,
807 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
809 [(set (vec.vt V128:$dst),
810 (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))],
811 vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
812 vec.prefix#"."#name, simdop, reqs>;
815 multiclass HalfPrecisionBinary<Vec vec, SDPatternOperator node, string name,
817 defm "" : SIMDBinary<vec, node, name, simdop, [HasHalfPrecision]>;
826 foreach vec = IntVecs in
827 def : Pat<(node (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
831 multiclass SIMDUnary<Vec vec, SDPatternOperator node, string name,
833 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins),
834 [(set (vec.vt V128:$dst),
835 (vec.vt (node (vec.vt V128:$v))))],
836 vec.prefix#"."#name#"\t$dst, $v",
837 vec.prefix#"."#name, simdop, reqs>;
840 multiclass HalfPrecisionUnary<Vec vec, SDPatternOperator node, string name,
842 defm "" : SIMDUnary<vec, node, name, simdop, [HasHalfPrecision]>;
848 foreach vec = IntVecs in
849 def : Pat<(vnot (vec.vt V128:$v)), (NOT $v)>;
865 foreach vec = AllVecs in
866 def : Pat<(vec.vt (int_wasm_bitselect
867 (vec.vt V128:$v1), (vec.vt V128:$v2), (vec.vt V128:$c))),
871 foreach vec = IntVecs in
872 def : Pat<(vec.vt (or (and (vec.vt V128:$c), (vec.vt V128:$v1)),
873 (and (vnot V128:$c), (vec.vt V128:$v2)))),
877 foreach vec = IntVecs in
878 def : Pat<(vec.vt (xor (and (xor (vec.vt V128:$v1), (vec.vt V128:$v2)),
879 (vec.vt V128:$c)),
880 (vec.vt V128:$v2))),
884 foreach vec = IntVecs in
885 def : Pat<(vec.vt (xor (and (xor (vec.vt V128:$v1), (vec.vt V128:$v2)),
886 (vnot (vec.vt V128:$c))),
887 (vec.vt V128:$v2))),
891 foreach vec = AllVecs in
892 def : Pat<(vec.vt (vselect
893 (vec.int_vt V128:$c), (vec.vt V128:$v1), (vec.vt V128:$v2))),
901 foreach vec = AllVecs in {
902 def : Pat<(select I32:$cond, (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
909 (i32 (setne I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
914 (i32 (seteq I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
916 } // foreach vec
942 defm ANYTRUE : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), [],
943 "v128.any_true\t$dst, $vec", "v128.any_true", 0x53>;
945 foreach vec = IntVecs in
946 def : Pat<(int_wasm_anytrue (vec.vt V128:$vec)), (ANYTRUE V128:$vec)>;
949 multiclass SIMDAllTrue<Vec vec, bits<32> simdop> {
950 defm ALLTRUE_#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
952 (i32 (int_wasm_alltrue (vec.vt V128:$vec))))],
953 vec.prefix#".all_true\t$dst, $vec",
954 vec.prefix#".all_true", simdop>;
975 defvar vec = !cast<Vec>(reduction[2]);
976 def : Pat<(i32 (and (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
977 def : Pat<(i32 (setne (i32 (intrinsic (vec.vt V128:$x))), (i32 0))), (inst $x)>;
978 def : Pat<(i32 (seteq (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
981 multiclass SIMDBitmask<Vec vec, bits<32> simdop> {
982 defm _#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
984 (i32 (int_wasm_bitmask (vec.vt V128:$vec))))],
985 vec.prefix#".bitmask\t$dst, $vec", vec.prefix#".bitmask",
998 multiclass SIMDShift<Vec vec, SDNode node, string name, bits<32> simdop> {
999 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x), (outs), (ins),
1000 [(set (vec.vt V128:$dst), (node V128:$vec, I32:$x))],
1001 vec.prefix#"."#name#"\t$dst, $vec, $x",
1002 vec.prefix#"."#name, simdop>;
1122 foreach vec = [I8x16, I16x8] in {
1123 defvar inst = !cast<NI>("AVGR_U_"#vec);
1126 (add_nuw (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
1127 (vec.splat (i32 1))),
1146 multiclass SIMDExtBinary<Vec vec, SDPatternOperator node, string name,
1148 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
1150 [(set (vec.vt V128:$dst), (node
1151 (vec.split.vt V128:$lhs),(vec.split.vt V128:$rhs)))],
1152 vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
1153 vec.prefix#"."#name, simdop>;
1289 foreach vec = [F32x4, F64x2, F16x8] in {
1290 defvar pmin = !cast<NI>("PMIN_"#vec);
1291 defvar pmax = !cast<NI>("PMAX_"#vec);
1292 def : Pat<(vec.int_vt (vselect
1293 (setolt (vec.vt (bitconvert V128:$rhs)),
1294 (vec.vt (bitconvert V128:$lhs))),
1297 def : Pat<(vec.int_vt (vselect
1298 (setolt (vec.vt (bitconvert V128:$lhs)),
1299 (vec.vt (bitconvert V128:$rhs))),
1322 multiclass SIMDConvert<Vec vec, Vec arg, SDPatternOperator op, string name,
1324 defm op#_#vec :
1325 SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
1326 [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
1327 vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop, reqs>;
1330 multiclass HalfPrecisionConvert<Vec vec, Vec arg, SDPatternOperator op,
1332 defm "" : SIMDConvert<vec, arg, op, name, simdop, [HasHalfPrecision]>;
1370 multiclass SIMDExtend<Vec vec, bits<32> baseInst> {
1371 defm "" : SIMDConvert<vec, vec.split, extend_low_s,
1372 "extend_low_"#vec.split.prefix#"_s", baseInst>;
1373 defm "" : SIMDConvert<vec, vec.split, extend_high_s,
1374 "extend_high_"#vec.split.prefix#"_s", !add(baseInst, 1)>;
1375 defm "" : SIMDConvert<vec, vec.split, extend_low_u,
1376 "extend_low_"#vec.split.prefix#"_u", !add(baseInst, 2)>;
1377 defm "" : SIMDConvert<vec, vec.split, extend_high_u,
1378 "extend_high_"#vec.split.prefix#"_u", !add(baseInst, 3)>;
1386 multiclass SIMDNarrow<Vec vec, bits<32> baseInst> {
1387 defvar name = vec.split.prefix#".narrow_"#vec.prefix;
1388 defm NARROW_S_#vec.split :
1390 [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_signed
1391 (vec.vt V128:$low), (vec.vt V128:$high))))],
1393 defm NARROW_U_#vec.split :
1395 [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_unsigned
1396 (vec.vt V128:$low), (vec.vt V128:$high))))],
1472 multiclass RelaxedConvert<Vec vec, Vec arg, SDPatternOperator op, string name, bits<32> simdop> {
1473 defm op#_#vec :
1474 RELAXED_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
1475 [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
1476 vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
1492 multiclass SIMDMADD<Vec vec, bits<32> simdopA, bits<32> simdopS, list<Predicate> reqs> {
1493 defm MADD_#vec :
1495 [(set (vec.vt V128:$dst), (int_wasm_relaxed_madd
1496 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1497 vec.prefix#".relaxed_madd\t$dst, $a, $b, $c",
1498 vec.prefix#".relaxed_madd", simdopA, reqs>;
1499 defm NMADD_#vec :
1501 [(set (vec.vt V128:$dst), (int_wasm_relaxed_nmadd
1502 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1503 vec.prefix#".relaxed_nmadd\t$dst, $a, $b, $c",
1504 vec.prefix#".relaxed_nmadd", simdopS, reqs>;
1515 multiclass SIMDLANESELECT<Vec vec, bits<32> op> {
1516 defm LANESELECT_#vec :
1518 [(set (vec.vt V128:$dst), (int_wasm_relaxed_laneselect
1519 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1520 vec.prefix#".relaxed_laneselect\t$dst, $a, $b, $c",
1521 vec.prefix#".relaxed_laneselect", op>;
1533 multiclass RelaxedBinary<Vec vec, SDPatternOperator node, string name,
1535 defm _#vec : RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
1537 [(set (vec.vt V128:$dst),
1538 (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))],
1539 vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
1540 vec.prefix#"."#name, simdop>;