Lines Matching +full:0 +full:xfd00
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
21 !if(!ge(simdop, 0x100),
22 !or(0xfd0000, !and(0xffff, simdop)),
23 !or(0xfd00, !and(0xff, simdop)))>,
66 def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
182 "v128.load\t$off$p2align", 0>;
187 "v128.load\t$off$p2align", 0>;
267 defvar loadpat = !cast<PatFrag>(exts[0]#vec.split.lane_bits);
291 defm "" : SIMDLoadZero<I32x4, 0x5c>;
292 defm "" : SIMDLoadZero<I64x2, 0x5d>;
306 (vector_insert (vec.splat (vec.lane_vt 0)), (vec.lane_vt (load $ptr)), 0)>;
331 defm "" : SIMDLoadLane<I8x16, 0x54>;
332 defm "" : SIMDLoadLane<I16x8, 0x55>;
333 defm "" : SIMDLoadLane<I32x4, 0x56>;
334 defm "" : SIMDLoadLane<I64x2, 0x57>;
342 (load_lane_a32 0, 0, imm:$idx, $addr, $vec)>,
346 (load_lane_a64 0, 0, imm:$idx, $addr, $vec)>,
412 defm "" : SIMDStoreLane<I8x16, 0x58>;
413 defm "" : SIMDStoreLane<I16x8, 0x59>;
414 defm "" : SIMDStoreLane<I32x4, 0x5a>;
415 defm "" : SIMDStoreLane<I64x2, 0x5b>;
421 (!cast<NI>("STORE_LANE_"#vec#"_A32") 0, $offset, imm:$idx, $addr, $vec)>,
426 (!cast<NI>("STORE_LANE_"#vec#"_A64") 0, $offset, imm:$idx, $addr, $vec)>,
622 "f16x8.splat\t$dst, $x", "f16x8.splat", 0x120>;
668 (and (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), (i32 0xff)),
674 (and (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), (i32 0xffff)),
683 "f16x8.extract_lane\t$idx", 0x121>;
707 (REPLACE_LANE_I8x16 $vec, 0, $x)>;
709 (REPLACE_LANE_I16x8 $vec, 0, $x)>;
711 (REPLACE_LANE_I32x4 $vec, 0, $x)>;
713 (REPLACE_LANE_I64x2 $vec, 0, $x)>;
715 (REPLACE_LANE_F32x4 $vec, 0, $x)>;
717 (REPLACE_LANE_F64x2 $vec, 0, $x)>;
793 def : Pat<(v4i32 (nodes[0] (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
798 def : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
899 "v128.select\t$dst, $lhs, $rhs, $cond", "v128.select", 0x1b>;
907 // a setne with 0 into a select.
909 (i32 (setne I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
914 (i32 (seteq I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
939 defm POPCNT : SIMDUnary<I8x16, ctpop, "popcnt", 0x62>;
943 "v128.any_true\t$dst, $vec", "v128.any_true", 0x53>;
957 defm "" : SIMDAllTrue<I8x16, 0x63>;
958 defm "" : SIMDAllTrue<I16x8, 0x83>;
959 defm "" : SIMDAllTrue<I32x4, 0xa3>;
960 defm "" : SIMDAllTrue<I64x2, 0xc3>;
962 // Reductions already return 0 or 1, so and 1, setne 0, and seteq 1
973 defvar intrinsic = !cast<Intrinsic>(reduction[0]);
977 def : Pat<(i32 (setne (i32 (intrinsic (vec.vt V128:$x))), (i32 0))), (inst $x)>;
1015 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>;
1140 def extend_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
1166 SIMDExtBinary<I16x8, extmul_low_s, "extmul_low_i8x16_s", 0x9c>;
1168 SIMDExtBinary<I16x8, extmul_high_s, "extmul_high_i8x16_s", 0x9d>;
1170 SIMDExtBinary<I16x8, extmul_low_u, "extmul_low_i8x16_u", 0x9e>;
1172 SIMDExtBinary<I16x8, extmul_high_u, "extmul_high_i8x16_u", 0x9f>;
1175 SIMDExtBinary<I32x4, extmul_low_s, "extmul_low_i16x8_s", 0xbc>;
1177 SIMDExtBinary<I32x4, extmul_high_s, "extmul_high_i16x8_s", 0xbd>;
1179 SIMDExtBinary<I32x4, extmul_low_u, "extmul_low_i16x8_u", 0xbe>;
1181 SIMDExtBinary<I32x4, extmul_high_u, "extmul_high_i16x8_u", 0xbf>;
1184 SIMDExtBinary<I64x2, extmul_low_s, "extmul_low_i32x4_s", 0xdc>;
1186 SIMDExtBinary<I64x2, extmul_high_s, "extmul_high_i32x4_s", 0xdd>;
1188 SIMDExtBinary<I64x2, extmul_low_u, "extmul_low_i32x4_u", 0xde>;
1190 SIMDExtBinary<I64x2, extmul_high_u, "extmul_high_i32x4_u", 0xdf>;
1215 defm CEIL : SIMDUnary<F32x4, fceil, "ceil", 0x67>;
1216 defm FLOOR : SIMDUnary<F32x4, ffloor, "floor", 0x68>;
1217 defm TRUNC: SIMDUnary<F32x4, ftrunc, "trunc", 0x69>;
1218 defm NEAREST: SIMDUnary<F32x4, fnearbyint, "nearest", 0x6a>;
1219 defm CEIL : SIMDUnary<F64x2, fceil, "ceil", 0x74>;
1220 defm FLOOR : SIMDUnary<F64x2, ffloor, "floor", 0x75>;
1221 defm TRUNC: SIMDUnary<F64x2, ftrunc, "trunc", 0x7a>;
1222 defm NEAREST: SIMDUnary<F64x2, fnearbyint, "nearest", 0x94>;
1223 defm CEIL : HalfPrecisionUnary<F16x8, fceil, "ceil", 0x13c>;
1224 defm FLOOR : HalfPrecisionUnary<F16x8, ffloor, "floor", 0x13d>;
1225 defm TRUNC : HalfPrecisionUnary<F16x8, ftrunc, "trunc", 0x13e>;
1226 defm NEAREST : HalfPrecisionUnary<F16x8, fnearbyint, "nearest", 0x13f>;
1338 defm "" : HalfPrecisionConvert<I16x8, F16x8, fp_to_sint, "trunc_sat_f16x8_s", 0x148>;
1339 defm "" : HalfPrecisionConvert<I16x8, F16x8, fp_to_uint, "trunc_sat_f16x8_u", 0x149>;
1347 def trunc_sat_zero_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
1353 0xfc>;
1355 0xfd>;
1358 def convert_low_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
1363 defm "" : SIMDConvert<F64x2, I32x4, convert_low_s, "convert_low_i32x4_s", 0xfe>;
1364 defm "" : SIMDConvert<F64x2, I32x4, convert_low_u, "convert_low_i32x4_u", 0xff>;
1365 defm "" : HalfPrecisionConvert<F16x8, I16x8, sint_to_fp, "convert_i16x8_s", 0x14a>;
1366 defm "" : HalfPrecisionConvert<F16x8, I16x8, uint_to_fp, "convert_i16x8_u", 0x14b>;
1381 defm "" : SIMDExtend<I16x8, 0x87>;
1382 defm "" : SIMDExtend<I32x4, 0xa7>;
1383 defm "" : SIMDExtend<I64x2, 0xc7>;
1420 "extadd_pairwise_i8x16_s", 0x7c>;
1422 "extadd_pairwise_i8x16_u", 0x7d>;
1424 "extadd_pairwise_i16x8_s", 0x7e>;
1426 "extadd_pairwise_i16x8_u", 0x7f>;
1429 def demote_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
1432 "demote_f64x2_zero", 0x5e>;
1434 def promote_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
1436 defm "" : SIMDConvert<F64x2, F32x4, promote_low, "promote_low_f32x4", 0x5f>;
1445 (promote_low_F64x2 (LOAD_ZERO_I64x2_A32 0, 0, I32:$addr))>,
1448 (promote_low_F64x2 (LOAD_ZERO_I64x2_A64 0, 0, I64:$addr))>,
1456 SIMDBinary<I16x8, int_wasm_q15mulr_sat_signed, "q15mulr_sat_s", 0x82>;
1466 "i8x16.relaxed_swizzle\t$dst, $src, $mask", "i8x16.relaxed_swizzle", 0x100>;
1480 "relaxed_trunc_f32x4_s", 0x101>;
1482 "relaxed_trunc_f32x4_u", 0x102>;
1484 "relaxed_trunc_f64x2_s_zero", 0x103>;
1486 "relaxed_trunc_f64x2_u_zero", 0x104>;
1507 defm "" : SIMDMADD<F32x4, 0x105, 0x106, [HasRelaxedSIMD]>;
1508 defm "" : SIMDMADD<F64x2, 0x107, 0x108, [HasRelaxedSIMD]>;
1509 defm "" : SIMDMADD<F16x8, 0x146, 0x147, [HasHalfPrecision]>;
1524 defm "" : SIMDLANESELECT<I8x16, 0x109>;
1525 defm "" : SIMDLANESELECT<I16x8, 0x10a>;
1526 defm "" : SIMDLANESELECT<I32x4, 0x10b>;
1527 defm "" : SIMDLANESELECT<I64x2, 0x10c>;
1544 RelaxedBinary<F32x4, int_wasm_relaxed_min, "relaxed_min", 0x10d>;
1546 RelaxedBinary<F32x4, int_wasm_relaxed_max, "relaxed_max", 0x10e>;
1548 RelaxedBinary<F64x2, int_wasm_relaxed_min, "relaxed_min", 0x10f>;
1550 RelaxedBinary<F64x2, int_wasm_relaxed_max, "relaxed_max", 0x110>;
1558 0x111>;
1569 "i16x8.relaxed_dot_i8x16_i7x16_s", 0x112>;
1577 "i32x4.relaxed_dot_i8x16_i7x16_add_s", 0x113>;
1589 "f32x4.relaxed_dot_bf16x8_add_f32", 0x114>;