Lines Matching refs:atomic
40 "memory.atomic.notify \t$dst, ${off}(${addr})${p2align}, $count",
41 "memory.atomic.notify \t${off}${p2align}", 0x00, false>;
46 "memory.atomic.notify \t$dst, ${off}(${addr})${p2align}, $count",
47 "memory.atomic.notify \t${off}${p2align}", 0x00, true>;
54 "memory.atomic.wait32 \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
55 "memory.atomic.wait32 \t${off}${p2align}", 0x01, false>;
61 "memory.atomic.wait32 \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
62 "memory.atomic.wait32 \t${off}${p2align}", 0x01, true>;
68 "memory.atomic.wait64 \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
69 "memory.atomic.wait64 \t${off}${p2align}", 0x02, false>;
75 "memory.atomic.wait64 \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
76 "memory.atomic.wait64 \t${off}${p2align}", 0x02, true>;
113 defm ATOMIC_FENCE : ATOMIC_NRI<(outs), (ins i8imm:$flags), [], "atomic.fence",
126 defm ATOMIC_LOAD_I32 : AtomicLoad<I32, "i32.atomic.load", 0x10>;
127 defm ATOMIC_LOAD_I64 : AtomicLoad<I64, "i64.atomic.load", 0x11>;
133 // Extending loads. Note that there are only zero-extending atomic loads, no
135 defm ATOMIC_LOAD8_U_I32 : AtomicLoad<I32, "i32.atomic.load8_u", 0x12>;
136 defm ATOMIC_LOAD16_U_I32 : AtomicLoad<I32, "i32.atomic.load16_u", 0x13>;
137 defm ATOMIC_LOAD8_U_I64 : AtomicLoad<I64, "i64.atomic.load8_u", 0x14>;
138 defm ATOMIC_LOAD16_U_I64 : AtomicLoad<I64, "i64.atomic.load16_u", 0x15>;
139 defm ATOMIC_LOAD32_U_I64 : AtomicLoad<I64, "i64.atomic.load32_u", 0x16>;
149 // Extension to i32 is elided by SelectionDAG as our atomic loads are
161 // We don't have single sext atomic load instructions. So for sext loads, we
180 // 32->64 sext load gets selected as i32.atomic.load, i64.extend_i32_s
192 defm ATOMIC_STORE_I32 : AtomicStore<I32, "i32.atomic.store", 0x17>;
193 defm ATOMIC_STORE_I64 : AtomicStore<I64, "i64.atomic.store", 0x18>;
195 // We used to need an 'atomic' version of store patterns because store and atomic_store
213 defm ATOMIC_STORE8_I32 : AtomicStore<I32, "i32.atomic.store8", 0x19>;
214 defm ATOMIC_STORE16_I32 : AtomicStore<I32, "i32.atomic.store16", 0x1a>;
215 defm ATOMIC_STORE8_I64 : AtomicStore<I64, "i64.atomic.store8", 0x1b>;
216 defm ATOMIC_STORE16_I64 : AtomicStore<I64, "i64.atomic.store16", 0x1c>;
217 defm ATOMIC_STORE32_I64 : AtomicStore<I64, "i64.atomic.store32", 0x1d>;
221 // We don't have single truncating atomic store instructions. For 32-bit
222 // instructions, we just need to match bare atomic stores. On the other hand,
258 defm ATOMIC_RMW_ADD_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.add", 0x1e>;
259 defm ATOMIC_RMW_ADD_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.add", 0x1f>;
261 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.add_u", 0x20>;
263 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.add_u", 0x21>;
265 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.add_u", 0x22>;
267 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.add_u", 0x23>;
269 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.add_u", 0x24>;
271 defm ATOMIC_RMW_SUB_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.sub", 0x25>;
272 defm ATOMIC_RMW_SUB_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.sub", 0x26>;
274 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.sub_u", 0x27>;
276 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.sub_u", 0x28>;
278 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.sub_u", 0x29>;
280 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.sub_u", 0x2a>;
282 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.sub_u", 0x2b>;
284 defm ATOMIC_RMW_AND_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.and", 0x2c>;
285 defm ATOMIC_RMW_AND_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.and", 0x2d>;
287 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.and_u", 0x2e>;
289 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.and_u", 0x2f>;
291 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.and_u", 0x30>;
293 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.and_u", 0x31>;
295 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.and_u", 0x32>;
297 defm ATOMIC_RMW_OR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.or", 0x33>;
298 defm ATOMIC_RMW_OR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.or", 0x34>;
300 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.or_u", 0x35>;
302 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.or_u", 0x36>;
304 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.or_u", 0x37>;
306 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.or_u", 0x38>;
308 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.or_u", 0x39>;
310 defm ATOMIC_RMW_XOR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.xor", 0x3a>;
311 defm ATOMIC_RMW_XOR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.xor", 0x3b>;
313 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xor_u", 0x3c>;
315 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xor_u", 0x3d>;
317 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xor_u", 0x3e>;
319 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xor_u", 0x3f>;
321 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xor_u", 0x40>;
324 WebAssemblyBinRMW<I32, "i32.atomic.rmw.xchg", 0x41>;
326 WebAssemblyBinRMW<I64, "i64.atomic.rmw.xchg", 0x42>;
328 WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xchg_u", 0x43>;
330 WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xchg_u", 0x44>;
332 WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xchg_u", 0x45>;
334 WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xchg_u", 0x46>;
336 WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xchg_u", 0x47>;
391 // 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s
465 WebAssemblyTerRMW<I32, "i32.atomic.rmw.cmpxchg", 0x48>;
467 WebAssemblyTerRMW<I64, "i64.atomic.rmw.cmpxchg", 0x49>;
469 WebAssemblyTerRMW<I32, "i32.atomic.rmw8.cmpxchg_u", 0x4a>;
471 WebAssemblyTerRMW<I32, "i32.atomic.rmw16.cmpxchg_u", 0x4b>;
473 WebAssemblyTerRMW<I64, "i64.atomic.rmw8.cmpxchg_u", 0x4c>;
475 WebAssemblyTerRMW<I64, "i64.atomic.rmw16.cmpxchg_u", 0x4d>;
477 WebAssemblyTerRMW<I64, "i64.atomic.rmw32.cmpxchg_u", 0x4e>;
525 // 32->64 sext RMW gets selected as i32.atomic.rmw.***, i64.extend_i32_s