Lines Matching refs:VecT
1917 MVT VecT = Extract.getOperand(0).getSimpleValueType(); in LowerSIGN_EXTEND_INREG() local
1918 if (VecT.getVectorElementType().getSizeInBits() > 32) in LowerSIGN_EXTEND_INREG()
1924 if (ExtractedVecT == VecT) in LowerSIGN_EXTEND_INREG()
1933 ExtractedVecT.getVectorNumElements() / VecT.getVectorNumElements(); in LowerSIGN_EXTEND_INREG()
2057 const EVT VecT = Op.getValueType(); in LowerBUILD_VECTOR() local
2060 bool CanSwizzle = VecT == MVT::v16i8; in LowerBUILD_VECTOR()
2111 VecT.getVectorNumElements()) in LowerBUILD_VECTOR()
2197 Result = DAG.getNode(WebAssemblyISD::SWIZZLE, DL, VecT, SwizzleSrc, in LowerBUILD_VECTOR()
2205 size_t DestLaneSize = VecT.getVectorElementType().getFixedSizeInBits() / 8; in LowerBUILD_VECTOR()
2206 size_t DestLaneCount = VecT.getVectorNumElements(); in LowerBUILD_VECTOR()
2210 SDValue Src2 = ShuffleSrc2 ? ShuffleSrc2 : DAG.getUNDEF(VecT); in LowerBUILD_VECTOR()
2211 if (Src1.getValueType() != VecT) { in LowerBUILD_VECTOR()
2216 Src1 = DAG.getBitcast(VecT, Src1); in LowerBUILD_VECTOR()
2218 if (Src2.getValueType() != VecT) { in LowerBUILD_VECTOR()
2223 Src2 = DAG.getBitcast(VecT, Src2); in LowerBUILD_VECTOR()
2240 Result = DAG.getVectorShuffle(VecT, DL, Src1, Src2, MaskRef); in LowerBUILD_VECTOR()
2273 Result = DAG.getBuildVector(VecT, DL, ConstLanes); in LowerBUILD_VECTOR()
2279 Result = DAG.getSplatBuildVector(VecT, DL, SplatValue); in LowerBUILD_VECTOR()
2292 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane, in LowerBUILD_VECTOR()