Lines Matching +full:64 +full:fs
43 // Alignments for 64 bit integers. in computeDataLayout()
44 Ret += "-i64:64"; in computeDataLayout()
46 // VE supports 32 bit and 64 bits integer on registers in computeDataLayout()
47 Ret += "-n32:64"; in computeDataLayout()
52 // Vector alignments are 64 bits in computeDataLayout()
55 Ret += "-v64:64:64"; // for v2f32 in computeDataLayout()
56 Ret += "-v128:64:64"; in computeDataLayout()
57 Ret += "-v256:64:64"; in computeDataLayout()
58 Ret += "-v512:64:64"; in computeDataLayout()
59 Ret += "-v1024:64:64"; in computeDataLayout()
60 Ret += "-v2048:64:64"; in computeDataLayout()
61 Ret += "-v4096:64:64"; in computeDataLayout()
62 Ret += "-v8192:64:64"; in computeDataLayout()
63 Ret += "-v16384:64:64"; // for v256f64 in computeDataLayout()
87 StringRef CPU, StringRef FS, in VETargetMachine() argument
92 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, in VETargetMachine()
96 Subtarget(TT, std::string(CPU), std::string(FS), *this) { in VETargetMachine()