Lines Matching +full:sw +full:- +full:exception
1 //===-- VERegisterInfo.td - VE Register defs ---------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
16 let HWEncoding{15-7} = 0;
17 let HWEncoding{6-0} = enc;
24 let HWEncoding{15-6} = 0;
25 let HWEncoding{5-0} = enc;
32 let HWEncoding{15-8} = 0;
33 let HWEncoding{7-0} = enc;
42 let HWEncoding{15-4} = 0;
43 let HWEncoding{3-0} = enc;
59 //-----------------------------------------------------------------------------
61 //-----------------------------------------------------------------------------
69 foreach I = 0-3 in
73 foreach I = 0-14 in
82 //-----------------------------------------------------------------------------
84 //-----------------------------------------------------------------------------
88 //-----------------------------------------------------------------------------
90 //-----------------------------------------------------------------------------
97 //-----------------------------------------------------------------------------
99 //-----------------------------------------------------------------------------
103 // Generic integer registers - 32 bits wide
104 foreach I = 0-63 in
105 def SW#I : VEReg<I, "sw"#I, [], ["s"#I]>, DwarfRegNum<[I]>;
107 // Generic floating point registers - 32 bits wide
108 // NOTE: Mark SF#I as alias of SW#I temporary to avoid register allocation
110 foreach I = 0-63 in
111 def SF#I : VEReg<I, "sf"#I, [], ["s"#I], [!cast<VEReg>("SW"#I)]>,
114 // Generic integer registers - 64 bits wide
126 foreach I = { 0-7, 12-13, 17-63 } in
127 def SX#I : VEReg<I, "s"#I, [!cast<VEReg>("SW"#I), !cast<VEReg>("SF"#I)],
131 // Aliases of the S* registers used to hold 128-bit for values (long doubles).
137 foreach I = 0-31 in
143 // Vector registers - 64 bits wide 256 elements
144 foreach I = 0-63 in
150 // Vector mask registers - 256 bits wide
153 foreach I = 1-15 in
161 foreach I = 1-7 in
174 (add (sequence "SW%u", 0, 7),
175 (sequence "SW%u", 34, 63),
176 (sequence "SW%u", 8, 33))>;