Lines Matching +full:32 +full:- +full:63
1 //===-- VERegisterInfo.td - VE Register defs ---------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
16 let HWEncoding{15-7} = 0;
17 let HWEncoding{6-0} = enc;
24 let HWEncoding{15-6} = 0;
25 let HWEncoding{5-0} = enc;
32 let HWEncoding{15-8} = 0;
33 let HWEncoding{7-0} = enc;
42 let HWEncoding{15-4} = 0;
43 let HWEncoding{3-0} = enc;
50 def sub_i32 : SubRegIndex<32, 32>; // Low 32 bit (32..63)
51 def sub_f32 : SubRegIndex<32>; // High 32 bit (0..31)
52 def sub_even : SubRegIndex<64>; // High 64 bit (0..63)
59 //-----------------------------------------------------------------------------
61 //-----------------------------------------------------------------------------
69 foreach I = 0-3 in
73 foreach I = 0-14 in
82 //-----------------------------------------------------------------------------
84 //-----------------------------------------------------------------------------
88 //-----------------------------------------------------------------------------
90 //-----------------------------------------------------------------------------
92 def VL : VEMiscReg<63, "vl">;
97 //-----------------------------------------------------------------------------
99 //-----------------------------------------------------------------------------
103 // Generic integer registers - 32 bits wide
104 foreach I = 0-63 in
107 // Generic floating point registers - 32 bits wide
110 foreach I = 0-63 in
114 // Generic integer registers - 64 bits wide
126 foreach I = { 0-7, 12-13, 17-63 } in
131 // Aliases of the S* registers used to hold 128-bit for values (long doubles).
137 foreach I = 0-31 in
143 // Vector registers - 64 bits wide 256 elements
144 foreach I = 0-63 in
150 // Vector mask registers - 256 bits wide
153 foreach I = 1-15 in
161 foreach I = 1-7 in
173 def I32 : RegisterClass<"VE", [i32], 32,
175 (sequence "SW%u", 34, 63),
179 (sequence "SX%u", 34, 63),
181 def F32 : RegisterClass<"VE", [f32], 32,
183 (sequence "SF%u", 34, 63),
194 (add (sequence "V%u", 0, 63),