Lines Matching full:sx
49 def SVMyi : Pseudo<(outs I64:$sx), (ins VM512:$vz, uimm3:$sy),
50 "# pseudo SVM $sx, $vz, $sy">;
92 // Define all vector instructions defined in SX-Aurora TSUBASA Architecture
168 defm VLDLSX : VLDm<"vldl.sx", 0x83, V64>;
178 defm VLDL2DSX : VLDm<"vldl2d.sx", 0xc3, V64>;
291 defm VGTLSX : VGTm<"vgtl.sx", 0xa3, V64>;
372 let sx = 0, vx = ?, hasSideEffects = 0 in
395 def vr : RR<opc, (outs I64:$sx), (ins RC:$vx, I64:$sy),
396 opcStr#" $sx, ${vx}(${sy})">;
398 def vi : RR<opc, (outs I64:$sx), (ins RC:$vx, uimm7:$sy),
399 opcStr#" $sx, ${vx}(${sy})">;
404 let sx = 0, vx = ?, hasSideEffects = 0 in
432 def mr : RR<opc, (outs I64:$sx), (ins RCM:$vz, I64:$sy),
433 opcStr#" $sx, $vz, $sy">;
435 def mi : RR<opc, (outs I64:$sx), (ins RCM:$vz, uimm2:$sy),
436 opcStr#" $sx, $vz, $sy">;
794 def "" : RV<opc, (outs I64:$sx), dag_in,
795 !strconcat(opcStr, " $sx,", argStr)> {
796 bits<7> sx;
797 let Inst{54-48} = sx;
800 def l : RV<opc, (outs I64:$sx), !con(dag_in, (ins I32:$vl)),
801 !strconcat(opcStr, " $sx,", argStr)> {
802 bits<7> sx;
803 let Inst{54-48} = sx;
805 def L : RV<opc, (outs I64:$sx), !con(dag_in, (ins VLS:$vl)),
806 !strconcat(opcStr, " $sx,", argStr)> {
807 bits<7> sx;
808 let Inst{54-48} = sx;
833 defm VADDSWSX : RVm<"vadds.w.sx", 0xca, V64, I32, VM>;
843 def : MnemonicAlias<"pvadds.lo.sx", "vadds.w.sx">;
867 defm VSUBSWSX : RVm<"vsubs.w.sx", 0xda, V64, I32, VM>;
877 def : MnemonicAlias<"pvsubs.lo.sx", "vsubs.w.sx">;
893 defm VMULSWSX : RVm<"vmuls.w.sx", 0xcb, V64, I32, VM>;
912 defm VDIVSWSX : RVDIVm<"vdivs.w.sx", 0xeb, V64, I32, VM>;
936 defm VCMPSWSX : RVm<"vcmps.w.sx", 0xfa, V64, I32, VM>;
946 def : MnemonicAlias<"pvcmps.lo.sx", "vcmps.w.sx">;
956 defm VMAXSWSX : RVm<"vmaxs.w.sx", 0x8a, V64, I32, VM>;
968 defm VMINSWSX : RVm<"vmins.w.sx", 0x8a, V64, I32, VM>;
979 def : MnemonicAlias<"pvmaxs.lo.sx", "vmaxs.w.sx">;
983 def : MnemonicAlias<"pvmins.lo.sx", "vmins.w.sx">;
1068 let cx = 0, cx2 = 0 in defm VSLAWSX : RVSm<"vsla.w.sx", 0xe6, I32, V64, VM>;
1075 def : MnemonicAlias<"pvsla.lo.sx", "vsla.w.sx">;
1084 let cx = 0, cx2 = 0 in defm VSRAWSX : RVSm<"vsra.w.sx", 0xf6, I32, V64, VM>;
1091 def : MnemonicAlias<"pvsra.lo.sx", "vsra.w.sx">;
1294 defm VCVTWDSX : RVFIXm<"vcvt.w.d.sx", 0xe8, V64, VM>;
1298 defm VCVTWSSX : RVFIXm<"vcvt.w.s.sx", 0xe8, V64, VM>;
1337 defm VSUMWSX : RVF1m<"vsum.w.sx", 0xea, V64, VM>;
1348 let cx2 = 0 in defm VRMAXSWFSTSX : RVF1m<"vrmaxs.w.fst.sx", 0xbb, V64, VM>;
1352 defm VRMAXSWLSTSX : RVF1m<"vrmaxs.w.lst.sx", 0xbb, V64, VM>;
1358 defm VRMINSWFSTSX : RVF1m<"vrmins.w.fst.sx", 0xbb, V64, VM>;
1363 defm VRMINSWLSTSX : RVF1m<"vrmins.w.lst.sx", 0xbb, V64, VM>;
1520 let sx = 0, cz = 0, sz = 0, hasSideEffects = 0, Defs = [VL] in {
1527 def SVL : RR<0x2f, (outs I64:$sx), (ins), "svl $sx">;
1531 def SMVL : RR<0x2e, (outs I64:$sx), (ins), "smvl $sx">;
1534 let sx = 0, cz = 0, sz = 0, hasSideEffects = 0, Defs = [VIX] in {