Lines Matching +full:in +full:-
1 //===----------------------------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
15 let mayLoad = 1, hasSideEffects = 0 in {
23 let mayStore = 1, hasSideEffects = 0 in {
32 //===----------------------------------------------------------------------===//
34 //===----------------------------------------------------------------------===//
37 let hasSideEffects = 0, isCodeGenOnly = 1 in {
38 let Constraints = "$vx = $vd", DisableEncoding = "$vd" in {
54 let hasSideEffects = 0, isCodeGenOnly = 1, DisableEncoding = "$vl" in {
56 "# pseudo-vfmk.at $vmx">;
58 "# pseudo-vfmk.af $vmx">;
61 "# pseudo-vfmk.w.$cf $vmx, $vz">;
64 "# pseudo-vfmk.w.$cf $vmx, $vz, $vm">;
67 "# pseudo-vfmk.s.$cf $vmx, $vz">;
70 "# pseudo-vfmk.s.$cf $vmx, $vz, $vm">;
74 let hasSideEffects = 0, isCodeGenOnly = 1 in {
89 //===----------------------------------------------------------------------===//
92 // Define all vector instructions defined in SX-Aurora TSUBASA Architecture
93 // Guide here. As those mnemonics, we use mnemonics defined in Vector Engine
106 // In order to represent above with a virtual register, we defines instructions
107 // with an additional base register and `_v` suffiex in mnemonic.
117 // with following suffixes in mnemonic.
121 //===----------------------------------------------------------------------===//
123 //-----------------------------------------------------------------------------
124 // Section 8.9 - Vector Load/Store and Move Instructions
125 //-----------------------------------------------------------------------------
128 let mayLoad = 1, hasSideEffects = 0, Uses = [VL] in
131 let DisableEncoding = disEnc in
135 isCodeGenOnly = 1 in
141 let isCodeGenOnly = 1, VE_VLInUse = 1 in {
146 let VE_VLIndex = 3 in
149 let cy = 0 in
151 let cz = 0 in
153 let cy = 0, cz = 0 in
157 let vc = 1 in defm "" : VLDtgm<opcStr, opc, RC>;
158 let vc = 0 in defm NC : VLDtgm<opcStr#".nc", opc, RC>;
161 // Section 8.9.1 - VLD (Vector Load)
164 // Section 8.9.2 - VLDU (Vector Load Upper)
167 // Section 8.9.3 - VLDL (Vector Load Lower)
169 let cx = 1 in defm VLDLZX : VLDm<"vldl.zx", 0x83, V64>;
171 // Section 8.9.4 - VLD2D (Vector Load 2D)
174 // Section 8.9.5 - VLDU2D (Vector Load Upper 2D)
177 // Section 8.9.6 - VLDL2D (Vector Load Lower 2D)
179 let cx = 1 in defm VLDL2DZX : VLDm<"vldl2d.zx", 0xc3, V64>;
182 let mayStore = 1, hasSideEffects = 0, Uses = [VL] in
185 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
194 let m = ?, VE_VLWithMask = 1 in
197 let VE_VLIndex = 3 in
200 let cy = 0 in
202 let cz = 0 in
204 let cy = 0, cz = 0 in
208 let vc = 1, cx = 0 in defm "" : VSTtgm<opcStr, opc, RC>;
209 let vc = 0, cx = 0 in defm NC : VSTtgm<opcStr#".nc", opc, RC>;
210 let vc = 1, cx = 1 in defm OT : VSTtgm<opcStr#".ot", opc, RC>;
211 let vc = 0, cx = 1 in defm NCOT : VSTtgm<opcStr#".nc.ot", opc, RC>;
214 // Section 8.9.7 - VST (Vector Store)
217 // Section 8.9.8 - VST (Vector Store Upper)
220 // Section 8.9.9 - VSTL (Vector Store Lower)
223 // Section 8.9.10 - VST2D (Vector Store 2D)
226 // Section 8.9.11 - VSTU2D (Vector Store Upper 2D)
229 // Section 8.9.12 - VSTL2D (Vector Store Lower 2D)
233 let mayLoad = 1, hasSideEffects = 0, Uses = [VL] in
236 let DisableEncoding = disEnc in
240 isCodeGenOnly = 1 in
247 let isCodeGenOnly = 1, VE_VLInUse = 1 in {
257 let m = ?, VE_VLWithMask = 1 in
260 let VE_VLIndex = 4 in
265 let cy = 0 in
268 let cz = 0 in
271 let cy = 0, cz = 0 in
276 let vy = ? in defm v : VGTlhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>;
277 let cs = 1, sw = ? in defm s : VGTlhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>;
280 let vc = 1 in defm "" : VGTtgm<opcStr, opc, RC>;
281 let vc = 0 in defm NC : VGTtgm<opcStr#".nc", opc, RC>;
284 // Section 8.9.13 - VGT (Vector Gather)
287 // Section 8.9.14 - VGTU (Vector Gather Upper)
290 // Section 8.9.15 - VGTL (Vector Gather Lower)
292 let cx = 1 in defm VGTLZX : VGTm<"vgtl.zx", 0xa3, V64>;
297 let mayStore = 1, hasSideEffects = 0, Uses = [VL] in
300 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
309 let m = ?, VE_VLWithMask = 1 in
312 let VE_VLIndex = 4 in
317 let cy = 0 in
320 let cz = 0 in
323 let cy = 0, cz = 0 in
328 let vy = ? in defm v : VSClhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>;
329 let cs = 1, sw = ? in defm s : VSClhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>;
332 let vc = 1, cx = 0 in defm "" : VSCtgm<opcStr, opc, RC>;
333 let vc = 0, cx = 0 in defm NC : VSCtgm<opcStr#".nc", opc, RC>;
334 let vc = 1, cx = 1 in defm OT : VSCtgm<opcStr#".ot", opc, RC>;
335 let vc = 0, cx = 1 in defm NCOT : VSCtgm<opcStr#".nc.ot", opc, RC>;
338 // Section 8.9.16 - VSC (Vector Scatter)
341 // Section 8.9.17 - VSCU (Vector Scatter Upper)
344 // Section 8.9.18 - VSCL (Vector Scatter Lower)
347 // Section 8.9.19 - PFCHV (Prefetch Vector)
348 let Uses = [VL] in
351 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
358 let VE_VLIndex = 2 in
361 let cy = 0 in
363 let cz = 0 in
365 let cy = 0, cz = 0 in
368 let vc = 1, vx = 0 in defm PFCHV : PFCHVm<"pfchv", 0x80>;
369 let vc = 0, vx = 0 in defm PFCHVNC : PFCHVm<"pfchv.nc", 0x80>;
371 // Section 8.9.20 - LSV (Load S to V)
372 let sx = 0, vx = ?, hasSideEffects = 0 in
377 isCodeGenOnly = 1 in
383 let cy = 0 in
385 let cz = 0 in
387 let cy = 0, cz = 0 in
392 // Section 8.9.21 - LVS (Load V to S)
393 let cz = 0, sz = 0, vx = ?, hasSideEffects = 0 in
397 let cy = 0 in
403 // Section 8.9.22 - LVM (Load VM)
404 let sx = 0, vx = ?, hasSideEffects = 0 in
410 isCodeGenOnly = 1 in {
417 let cy = 0 in
419 let cz = 0 in
421 let cy = 0, cz = 0 in
429 // Section 8.9.23 - SVM (Save VM)
430 let cz = 0, sz = 0, vz = ?, hasSideEffects = 0 in
434 let cy = 0 in
440 // Section 8.9.24 - VBRD (Vector Broadcast)
441 let vx = ?, hasSideEffects = 0, Uses = [VL] in
444 let DisableEncoding = disEnc in
448 isCodeGenOnly = 1 in
455 let isCodeGenOnly = 1, VE_VLInUse = 1 in {
465 let m = ?, VE_VLWithMask = 1 in
468 let VE_VLIndex = 2 in
472 let cy = 0 in
475 let cx = 0, cx2 = 0 in
477 let cx = 0, cx2 = 1 in
479 let cx = 1, cx2 = 0 in
481 let cx = 1, cx2 = 1 in
484 // Section 8.9.25 - VMV (Vector Move)
485 let vx = ?, vz = ?, hasSideEffects = 0, Uses = [VL] in
488 let DisableEncoding = disEnc in
492 isCodeGenOnly = 1 in
499 let isCodeGenOnly = 1, VE_VLInUse = 1 in {
509 let m = ?, VE_VLWithMask = 1 in
512 let VE_VLIndex = 3 in
516 let cy = 0 in
521 //-----------------------------------------------------------------------------
522 // Section 8.10 - Vector Fixed-Point Arithmetic Instructions
523 //-----------------------------------------------------------------------------
526 let vx = ?, hasSideEffects = 0, Uses = [VL] in
529 let DisableEncoding = disEnc in
533 isCodeGenOnly = 1 in
540 let isCodeGenOnly = 1, VE_VLInUse = 1 in {
550 let m = ?, VE_VLWithMask = 1 in
555 let VE_VLIndex = 3 in
558 let cy = 0, sy = 0, vy = ?, vz = ? in
560 let cs = 1, vz = ? in
562 let cs = 1, cy = 0, vz = ? in
567 let VE_VLIndex = 3 in
570 let cy = 0, sy = 0, vy = ?, vz = ? in
572 let cs2 = 1, vy = ? in
574 let cs2 = 1, cy = 0, vy = ? in
576 let cs = 1, vz = ? in
578 let cs = 1, cy = 0, vz = ? in
583 let VE_VLIndex = 3 in
586 let cy = 0, sy = 0, vy = ?, vz = ? in
588 let cs = 1, vz = ? in
590 let cs = 1, cy = 0, vz = ? in
595 let VE_VLIndex = 2 in
598 let cy = 0, sy = 0, vz = ? in
603 let VE_VLIndex = 1 in
606 let cy = 0, sy = 0 in
611 let VE_VLIndex = 3 in
614 let cy = 0, sy = 0, vy = ?, vz = ? in
616 let cs = 1, vz = ? in
618 let cs = 1, cy = 0, vz = ? in
623 let VE_VLIndex = 4 in
626 let vy = ?, vz = ? in
629 let cy = 0, vy = ?, vz = ? in
635 let VE_VLIndex = 4 in
638 let cz = 1, sz = ?, vz = ? in
641 let cz = 0, sz = ?, vz = ? in
644 let cy = 0, cz = 1, sz = ?, vz = ? in
647 let cy = 0, cz = 0, sz = ?, vz = ? in
653 let VE_VLIndex = 2 in
656 let cy = 0, sy = 0, vy = ? in
661 let VE_VLIndex = 4 in
664 let cy = 0, sy = 0, vy = ?, vz = ?, vw = ? in
667 let cs2 = 1, vy = ?, vw = ? in
670 let cs2 = 1, cy = 0, vy = ?, vw = ? in
673 let cs = 1, vz = ?, vw = ? in
676 let cs = 1, cy = 0, vz = ?, vw = ? in
682 let hasSideEffects = 0, VE_VLIndex = 3 in
685 let cy = 0, sy = 0, vy = ?, vz = ? in
689 let vx = ?, hasSideEffects = 0, Uses = [VL] in
692 let DisableEncoding = disEnc in
695 let isCodeGenOnly = 1, Constraints = "$vx = $base", DisableEncoding = disEnc#"$base" in
702 let isCodeGenOnly = 1, VE_VLInUse = 1 in {
711 let VE_VLIndex = 3 in
714 let vy = ? in
716 let cy = 0, vy = ? in
721 let VE_VLIndex = 4 in
724 let vy = ?, vz = ? in
727 let cy = 0, vy = ?, vz = ? in
733 let vy = ?, vz = ?, VE_VLIndex = 4 in
738 let cy = 0 in defm vvi : RVlm<opcStr, ", $vy, $vz, $sy", opc, RC,
742 let vx = ?, hasSideEffects = 0, Uses = [VL] in
746 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
756 let m = ?, VE_VLWithMask = 1 in
762 let cy = 0, sy = 0 in
765 let vy = ?, vz = ?, VE_VLIndex = 3 in
767 let vy = 15 /* AT */, VE_VLIndex = 1 in
769 let vy = 0 /* AF */, VE_VLIndex = 1 in
778 let cy = 0, sy = 0, vx = ?, vy = ?, vz = ?, hasSideEffects = 0 in
785 let cy = 0, sy = 0, vx = ?, vy = ?, hasSideEffects = 0 in
792 let cy = 0, sy = 0, vy = ?, hasSideEffects = 0, Uses = [VL] in
797 let Inst{54-48} = sx;
799 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
803 let Inst{54-48} = sx;
808 let Inst{54-48} = sx;
812 let VE_VLIndex = 2 in
817 // Section 8.10.1 - VADD (Vector Add)
818 let cx = 0, cx2 = 0 in
820 let cx = 0, cx2 = 1 in {
822 let isCodeGenOnly = 1 in
825 let cx = 1, cx2 = 0 in
827 let cx = 1, cx2 = 1 in
831 // Section 8.10.2 - VADS (Vector Add Single)
832 let cx = 0, cx2 = 0 in
834 let cx = 0, cx2 = 1 in {
836 let isCodeGenOnly = 1 in
839 let cx = 1, cx2 = 0 in
841 let cx = 1, cx2 = 1 in
848 // Section 8.10.3 - VADX (Vector Add)
851 // Section 8.10.4 - VSUB (Vector Subtract)
852 let cx = 0, cx2 = 0 in
854 let cx = 0, cx2 = 1 in {
856 let isCodeGenOnly = 1 in
859 let cx = 1, cx2 = 0 in
861 let cx = 1, cx2 = 1 in
865 // Section 8.10.5 - VSBS (Vector Subtract Single)
866 let cx = 0, cx2 = 0 in
868 let cx = 0, cx2 = 1 in {
870 let isCodeGenOnly = 1 in
873 let cx = 1, cx2 = 0 in
875 let cx = 1, cx2 = 1 in
882 // Section 8.10.6 - VSBX (Vector Subtract)
885 // Section 8.10.7 - VMPY (Vector Multiply)
886 let cx2 = 0 in
888 let cx2 = 1 in
891 // Section 8.10.8 - VMPS (Vector Multiply Single)
892 let cx2 = 0 in
894 let cx2 = 1 in
898 // Section 8.10.9 - VMPX (Vector Multiply)
901 // Section 8.10.10 - VMPD (Vector Multiply)
904 // Section 8.10.11 - VDIV (Vector Divide)
905 let cx2 = 0 in
907 let cx2 = 1 in
910 // Section 8.10.12 - VDVS (Vector Divide Single)
911 let cx2 = 0 in
913 let cx2 = 1 in
917 // Section 8.10.13 - VDVX (Vector Divide)
920 // Section 8.10.14 - VCMP (Vector Compare)
921 let cx = 0, cx2 = 0 in
923 let cx = 0, cx2 = 1 in {
925 let isCodeGenOnly = 1 in
928 let cx = 1, cx2 = 0 in
930 let cx = 1, cx2 = 1 in
934 // Section 8.10.15 - VCPS (Vector Compare Single)
935 let cx = 0, cx2 = 0 in
937 let cx = 0, cx2 = 1 in {
939 let isCodeGenOnly = 1 in
942 let cx = 1, cx2 = 0 in
944 let cx = 1, cx2 = 1 in
951 // Section 8.10.16 - VCPX (Vector Compare)
954 // Section 8.10.17 - VCMS (Vector Compare and Select Maximum/Minimum Single)
955 let cx = 0, cx2 = 0 in
957 let cx = 0, cx2 = 1 in {
959 let isCodeGenOnly = 1 in
962 let cx = 1, cx2 = 0 in
964 let cx = 1, cx2 = 1 in
966 let cs2 = 1 in {
967 let cx = 0, cx2 = 0 in
969 let cx = 0, cx2 = 1 in {
971 let isCodeGenOnly = 1 in
974 let cx = 1, cx2 = 0 in
976 let cx = 1, cx2 = 1 in
988 // Section 8.10.18 - VCMX (Vector Compare and Select Maximum/Minimum)
990 let cs2 = 1 in
993 //-----------------------------------------------------------------------------
994 // Section 8.11 - Vector Logical Operation Instructions
995 //-----------------------------------------------------------------------------
997 // Section 8.11.1 - VAND (Vector And)
998 let cx = 0, cx2 = 0 in defm VAND : RVLm<"vand", 0xc4, I64, V64, VM>;
999 let cx = 0, cx2 = 1 in defm PVANDLO : RVLm<"pvand.lo", 0xc4, I32, V64, VM>;
1000 let cx = 1, cx2 = 0 in defm PVANDUP : RVLm<"pvand.up", 0xc4, F32, V64, VM>;
1001 let cx = 1, cx2 = 1 in defm PVAND : RVLm<"pvand", 0xc4, I64, V64, VM512>;
1003 // Section 8.11.2 - VOR (Vector Or)
1004 let cx = 0, cx2 = 0 in defm VOR : RVLm<"vor", 0xc5, I64, V64, VM>;
1005 let cx = 0, cx2 = 1 in defm PVORLO : RVLm<"pvor.lo", 0xc5, I32, V64, VM>;
1006 let cx = 1, cx2 = 0 in defm PVORUP : RVLm<"pvor.up", 0xc5, F32, V64, VM>;
1007 let cx = 1, cx2 = 1 in defm PVOR : RVLm<"pvor", 0xc5, I64, V64, VM512>;
1009 // Section 8.11.3 - VXOR (Vector Exclusive Or)
1010 let cx = 0, cx2 = 0 in defm VXOR : RVLm<"vxor", 0xc6, I64, V64, VM>;
1011 let cx = 0, cx2 = 1 in defm PVXORLO : RVLm<"pvxor.lo", 0xc6, I32, V64, VM>;
1012 let cx = 1, cx2 = 0 in defm PVXORUP : RVLm<"pvxor.up", 0xc6, F32, V64, VM>;
1013 let cx = 1, cx2 = 1 in defm PVXOR : RVLm<"pvxor", 0xc6, I64, V64, VM512>;
1015 // Section 8.11.4 - VEQV (Vector Equivalence)
1016 let cx = 0, cx2 = 0 in defm VEQV : RVLm<"veqv", 0xc7, I64, V64, VM>;
1017 let cx = 0, cx2 = 1 in defm PVEQVLO : RVLm<"pveqv.lo", 0xc7, I32, V64, VM>;
1018 let cx = 1, cx2 = 0 in defm PVEQVUP : RVLm<"pveqv.up", 0xc7, F32, V64, VM>;
1019 let cx = 1, cx2 = 1 in defm PVEQV : RVLm<"pveqv", 0xc7, I64, V64, VM512>;
1021 // Section 8.11.5 - VLDZ (Vector Leading Zero Count)
1022 let cx = 0, cx2 = 0 in defm VLDZ : RV1m<"vldz", 0xe7, V64, VM>;
1023 let cx = 0, cx2 = 1 in defm PVLDZLO : RV1m<"pvldz.lo", 0xe7, V64, VM>;
1024 let cx = 1, cx2 = 0 in defm PVLDZUP : RV1m<"pvldz.up", 0xe7, V64, VM>;
1025 let cx = 1, cx2 = 1 in defm PVLDZ : RV1m<"pvldz", 0xe7, V64, VM512>;
1027 // Section 8.11.6 - VPCNT (Vector Population Count)
1028 let cx = 0, cx2 = 0 in defm VPCNT : RV1m<"vpcnt", 0xac, V64, VM>;
1029 let cx = 0, cx2 = 1 in defm PVPCNTLO : RV1m<"pvpcnt.lo", 0xac, V64, VM>;
1030 let cx = 1, cx2 = 0 in defm PVPCNTUP : RV1m<"pvpcnt.up", 0xac, V64, VM>;
1031 let cx = 1, cx2 = 1 in defm PVPCNT : RV1m<"pvpcnt", 0xac, V64, VM512>;
1033 // Section 8.11.7 - VBRV (Vector Bit Reverse)
1034 let cx = 0, cx2 = 0 in defm VBRV : RV1m<"vbrv", 0xf7, V64, VM>;
1035 let cx = 0, cx2 = 1 in defm PVBRVLO : RV1m<"pvbrv.lo", 0xf7, V64, VM>;
1036 let cx = 1, cx2 = 0 in defm PVBRVUP : RV1m<"pvbrv.up", 0xf7, V64, VM>;
1037 let cx = 1, cx2 = 1 in defm PVBRV : RV1m<"pvbrv", 0xf7, V64, VM512>;
1039 // Section 8.11.8 - VSEQ (Vector Sequential Number)
1040 let cx = 0, cx2 = 0 in defm VSEQ : RV0m<"vseq", 0x99, V64, VM>;
1041 let cx = 0, cx2 = 1 in defm PVSEQLO : RV0m<"pvseq.lo", 0x99, V64, VM>;
1042 let cx = 1, cx2 = 0 in defm PVSEQUP : RV0m<"pvseq.up", 0x99, V64, VM>;
1043 let cx = 1, cx2 = 1 in defm PVSEQ : RV0m<"pvseq", 0x99, V64, VM512>;
1045 //-----------------------------------------------------------------------------
1046 // Section 8.12 - Vector Shift Operation Instructions
1047 //-----------------------------------------------------------------------------
1049 // Section 8.12.1 - VSLL (Vector Shift Left Logical)
1050 let cx = 0, cx2 = 0 in defm VSLL : RVSm<"vsll", 0xe5, I64, V64, VM>;
1051 let cx = 0, cx2 = 1 in defm PVSLLLO : RVSm<"pvsll.lo", 0xe5, I32, V64, VM>;
1052 let cx = 1, cx2 = 0 in defm PVSLLUP : RVSm<"pvsll.up", 0xe5, F32, V64, VM>;
1053 let cx = 1, cx2 = 1 in defm PVSLL : RVSm<"pvsll", 0xe5, I64, V64, VM512>;
1055 // Section 8.12.2 - VSLD (Vector Shift Left Double)
1058 // Section 8.12.3 - VSRL (Vector Shift Right Logical)
1059 let cx = 0, cx2 = 0 in defm VSRL : RVSm<"vsrl", 0xf5, I64, V64, VM>;
1060 let cx = 0, cx2 = 1 in defm PVSRLLO : RVSm<"pvsrl.lo", 0xf5, I32, V64, VM>;
1061 let cx = 1, cx2 = 0 in defm PVSRLUP : RVSm<"pvsrl.up", 0xf5, F32, V64, VM>;
1062 let cx = 1, cx2 = 1 in defm PVSRL : RVSm<"pvsrl", 0xf5, I64, V64, VM512>;
1064 // Section 8.12.4 - VSRD (Vector Shift Right Double)
1067 // Section 8.12.5 - VSLA (Vector Shift Left Arithmetic)
1068 let cx = 0, cx2 = 0 in defm VSLAWSX : RVSm<"vsla.w.sx", 0xe6, I32, V64, VM>;
1069 let cx = 0, cx2 = 1 in {
1071 let isCodeGenOnly = 1 in defm VSLAWZX : RVSm<"vsla.w.zx", 0xe6, I32, V64, VM>;
1073 let cx = 1, cx2 = 0 in defm PVSLAUP : RVSm<"pvsla.up", 0xe6, F32, V64, VM>;
1074 let cx = 1, cx2 = 1 in defm PVSLA : RVSm<"pvsla", 0xe6, I64, V64, VM512>;
1080 // Section 8.12.6 - VSLAX (Vector Shift Left Arithmetic)
1083 // Section 8.12.7 - VSRA (Vector Shift Right Arithmetic)
1084 let cx = 0, cx2 = 0 in defm VSRAWSX : RVSm<"vsra.w.sx", 0xf6, I32, V64, VM>;
1085 let cx = 0, cx2 = 1 in {
1087 let isCodeGenOnly = 1 in defm VSRAWZX : RVSm<"vsra.w.zx", 0xf6, I32, V64, VM>;
1089 let cx = 1, cx2 = 0 in defm PVSRAUP : RVSm<"pvsra.up", 0xf6, F32, V64, VM>;
1090 let cx = 1, cx2 = 1 in defm PVSRA : RVSm<"pvsra", 0xf6, I64, V64, VM512>;
1096 // Section 8.12.8 - VSRAX (Vector Shift Right Arithmetic)
1099 // Section 8.12.9 - VSFA (Vector Shift Left and Add)
1102 //-----------------------------------------------------------------------------
1103 // Section 8.13 - Vector Floating-Point Arithmetic Instructions
1104 //-----------------------------------------------------------------------------
1106 // Section 8.13.1 - VFAD (Vector Floating Add)
1107 let cx = 0, cx2 = 0 in
1109 let cx = 0, cx2 = 1 in
1111 let cx = 1, cx2 = 0 in {
1113 let isCodeGenOnly = 1 in
1116 let cx = 1, cx2 = 1 in
1120 // Section 8.13.2 - VFSB (Vector Floating Subtract)
1121 let cx = 0, cx2 = 0 in
1123 let cx = 0, cx2 = 1 in
1125 let cx = 1, cx2 = 0 in {
1127 let isCodeGenOnly = 1 in
1130 let cx = 1, cx2 = 1 in
1134 // Section 8.13.3 - VFMP (Vector Floating Multiply)
1135 let cx = 0, cx2 = 0 in
1137 let cx = 0, cx2 = 1 in
1139 let cx = 1, cx2 = 0 in {
1141 let isCodeGenOnly = 1 in
1144 let cx = 1, cx2 = 1 in
1148 // Section 8.13.4 - VFDV (Vector Floating Divide)
1150 let cx = 1 in
1153 // Section 8.13.5 - VFSQRT (Vector Floating Square Root)
1155 let cx = 1 in
1158 // Section 8.13.6 - VFCP (Vector Floating Compare)
1159 let cx = 0, cx2 = 0 in
1161 let cx = 0, cx2 = 1 in
1163 let cx = 1, cx2 = 0 in {
1165 let isCodeGenOnly = 1 in
1168 let cx = 1, cx2 = 1 in
1172 // Section 8.13.7 - VFCM (Vector Floating Compare and Select Maximum/Minimum)
1173 let cx = 0, cx2 = 0 in
1175 let cx = 0, cx2 = 1 in
1177 let cx = 1, cx2 = 0 in {
1179 let isCodeGenOnly = 1 in
1182 let cx = 1, cx2 = 1 in
1184 let cs2 = 1 in {
1185 let cx = 0, cx2 = 0 in
1187 let cx = 0, cx2 = 1 in
1189 let cx = 1, cx2 = 0 in {
1191 let isCodeGenOnly = 1 in
1194 let cx = 1, cx2 = 1 in
1200 // Section 8.13.8 - VFMAD (Vector Floating Fused Multiply Add)
1201 let cx = 0, cx2 = 0 in
1203 let cx = 0, cx2 = 1 in
1205 let cx = 1, cx2 = 0 in {
1207 let isCodeGenOnly = 1 in
1210 let cx = 1, cx2 = 1 in
1214 // Section 8.13.9 - VFMSB (Vector Floating Fused Multiply Subtract)
1215 let cx = 0, cx2 = 0 in
1217 let cx = 0, cx2 = 1 in
1219 let cx = 1, cx2 = 0 in {
1221 let isCodeGenOnly = 1 in
1224 let cx = 1, cx2 = 1 in
1228 // Section 8.13.10 - VFNMAD (Vector Floating Fused Negative Multiply Add)
1229 let cx = 0, cx2 = 0 in
1231 let cx = 0, cx2 = 1 in
1233 let cx = 1, cx2 = 0 in {
1235 let isCodeGenOnly = 1 in
1238 let cx = 1, cx2 = 1 in
1242 // Section 8.13.11 - VFNMSB (Vector Floating Fused Negative Multiply Subtract)
1243 let cx = 0, cx2 = 0 in
1245 let cx = 0, cx2 = 1 in
1247 let cx = 1, cx2 = 0 in {
1249 let isCodeGenOnly = 1 in
1252 let cx = 1, cx2 = 1 in
1256 // Section 8.13.12 - VRCP (Vector Floating Reciprocal)
1257 let cx = 0, cx2 = 0 in defm VRCPD : RVF1m<"vrcp.d", 0xe1, V64, VM>;
1258 let cx = 0, cx2 = 1 in defm PVRCPLO : RVF1m<"pvrcp.lo", 0xe1, V64, VM>;
1259 let cx = 1, cx2 = 0 in {
1261 let isCodeGenOnly = 1 in defm VRCPS : RVF1m<"vrcp.s", 0xe1, V64, VM>;
1263 let cx = 1, cx2 = 1 in defm PVRCP : RVF1m<"pvrcp", 0xe1, V64, VM512>;
1266 // Section 8.13.13 - VRSQRT (Vector Floating Reciprocal Square Root)
1267 let cx = 0, cx2 = 0 in defm VRSQRTD : RVF1m<"vrsqrt.d", 0xf1, V64, VM>;
1268 let cx = 0, cx2 = 1 in defm PVRSQRTLO : RVF1m<"pvrsqrt.lo", 0xf1, V64, VM>;
1269 let cx = 1, cx2 = 0 in {
1271 let isCodeGenOnly = 1 in
1274 let cx = 1, cx2 = 1 in
1276 let cs2 = 1 in {
1277 let cx = 0, cx2 = 0 in
1279 let cx = 0, cx2 = 1 in
1281 let cx = 1, cx2 = 0 in {
1283 let isCodeGenOnly = 1 in
1286 let cx = 1, cx2 = 1 in
1292 // Section 8.13.14 - VFIX (Vector Convert to Fixed Pointer)
1293 let cx = 0, cx2 = 0, cs2 = 0 in
1295 let cx = 0, cx2 = 1, cs2 = 0 in
1297 let cx = 1, cx2 = 0, cs2 = 0 in
1299 let cx = 1, cx2 = 1, cs2 = 0 in
1301 let cx = 0, cx2 = 1, cs2 = 1 in
1303 let cx = 1, cx2 = 0, cs2 = 1 in
1305 let cx = 1, cx2 = 1, cs2 = 1 in
1308 // Section 8.13.15 - VFIXX (Vector Convert to Fixed Pointer)
1311 // Section 8.13.16 - VFLT (Vector Convert to Floating Pointer)
1312 let cx = 0, cx2 = 0, cs2 = 0 in
1314 let cx = 1, cx2 = 0, cs2 = 0 in
1316 let cx = 0, cx2 = 1, cs2 = 1 in
1318 let cx = 1, cx2 = 0, cs2 = 1 in
1320 let cx = 1, cx2 = 1, cs2 = 1 in
1323 // Section 8.13.17 - VFLTX (Vector Convert to Floating Pointer)
1326 // Section 8.13.18 - VCVS (Vector Convert to Single-format)
1329 // Section 8.13.19 - VCVD (Vector Convert to Double-format)
1332 //-----------------------------------------------------------------------------
1333 // Section 8.14 - Vector Reduction Instructions
1334 //-----------------------------------------------------------------------------
1336 // Section 8.14.1 - VSUMS (Vector Sum Single)
1338 let cx2 = 1 in defm VSUMWZX : RVF1m<"vsum.w.zx", 0xea, V64, VM>;
1340 // Section 8.14.2 - VSUMX (Vector Sum)
1343 // Section 8.14.3 - VFSUM (Vector Floating Sum)
1345 let cx = 1 in defm VFSUMS : RVF1m<"vfsum.s", 0xec, V64, VM>;
1347 // Section 8.14.4 - VMAXS (Vector Maximum/Minimum Single)
1348 let cx2 = 0 in defm VRMAXSWFSTSX : RVF1m<"vrmaxs.w.fst.sx", 0xbb, V64, VM>;
1349 let cx2 = 1 in defm VRMAXSWFSTZX : RVF1m<"vrmaxs.w.fst.zx", 0xbb, V64, VM>;
1350 let cs = 1 in {
1351 let cx2 = 0 in
1353 let cx2 = 1 in
1356 let cs2 = 1 in {
1357 let cx2 = 0 in
1359 let cx2 = 1 in
1361 let cs = 1 in {
1362 let cx2 = 0 in
1364 let cx2 = 1 in
1369 // Section 8.14.5 - VMAXX (Vector Maximum/Minimum)
1370 let cs = 0 in defm VRMAXSLFST : RVF1m<"vrmaxs.l.fst", 0xab, V64, VM>;
1371 let cs = 1 in defm VRMAXSLLST : RVF1m<"vrmaxs.l.lst", 0xab, V64, VM>;
1372 let cs2 = 1 in {
1373 let cs = 0 in defm VRMINSLFST : RVF1m<"vrmins.l.fst", 0xab, V64, VM>;
1374 let cs = 1 in defm VRMINSLLST : RVF1m<"vrmins.l.lst", 0xab, V64, VM>;
1377 // Section 8.14.6 - VFMAX (Vector Floating Maximum/Minimum)
1378 let cs = 0 in defm VFRMAXDFST : RVF1m<"vfrmax.d.fst", 0xad, V64, VM>;
1379 let cs = 1 in defm VFRMAXDLST : RVF1m<"vfrmax.d.lst", 0xad, V64, VM>;
1380 let cs2 = 1 in {
1381 let cs = 0 in defm VFRMINDFST : RVF1m<"vfrmin.d.fst", 0xad, V64, VM>;
1382 let cs = 1 in defm VFRMINDLST : RVF1m<"vfrmin.d.lst", 0xad, V64, VM>;
1384 let cx = 1 in {
1385 let cs = 0 in defm VFRMAXSFST : RVF1m<"vfrmax.s.fst", 0xad, V64, VM>;
1386 let cs = 1 in defm VFRMAXSLST : RVF1m<"vfrmax.s.lst", 0xad, V64, VM>;
1387 let cs2 = 1 in {
1388 let cs = 0 in defm VFRMINSFST : RVF1m<"vfrmin.s.fst", 0xad, V64, VM>;
1389 let cs = 1 in defm VFRMINSLST : RVF1m<"vfrmin.s.lst", 0xad, V64, VM>;
1393 // Section 8.14.7 - VRAND (Vector Reduction And)
1396 // Section 8.14.8 - VROR (Vector Reduction Or)
1399 // Section 8.14.9 - VRXOR (Vector Reduction Exclusive Or)
1402 //-----------------------------------------------------------------------------
1403 // Section 8.15 - Vector Iterative Operation Instructions
1404 //-----------------------------------------------------------------------------
1406 // Section 8.15.1 - VFIA (Vector Floating Iteration Add)
1407 let cx = 0 in defm VFIAD : RVI2m<"vfia.d", 0xce, V64, I64>;
1408 let cx = 1 in defm VFIAS : RVI2m<"vfia.s", 0xce, V64, F32>;
1410 // Section 8.15.2 - VFIS (Vector Floating Iteration Subtract)
1411 let cx = 0 in defm VFISD : RVI2m<"vfis.d", 0xde, V64, I64>;
1412 let cx = 1 in defm VFISS : RVI2m<"vfis.s", 0xde, V64, F32>;
1414 // Section 8.15.3 - VFIM (Vector Floating Iteration Multiply)
1415 let cx = 0 in defm VFIMD : RVI2m<"vfim.d", 0xcf, V64, I64>;
1416 let cx = 1 in defm VFIMS : RVI2m<"vfim.s", 0xcf, V64, F32>;
1418 // Section 8.15.4 - VFIAM (Vector Floating Iteration Add and Multiply)
1419 let cx = 0 in defm VFIAMD : RVI3m<"vfiam.d", 0xee, V64, I64>;
1420 let cx = 1 in defm VFIAMS : RVI3m<"vfiam.s", 0xee, V64, F32>;
1422 // Section 8.15.5 - VFISM (Vector Floating Iteration Subtract and Multiply)
1423 let cx = 0 in defm VFISMD : RVI3m<"vfism.d", 0xfe, V64, I64>;
1424 let cx = 1 in defm VFISMS : RVI3m<"vfism.s", 0xfe, V64, F32>;
1426 // Section 8.15.6 - VFIMA (Vector Floating Iteration Multiply and Add)
1427 let cx = 0 in defm VFIMAD : RVI3m<"vfima.d", 0xef, V64, I64>;
1428 let cx = 1 in defm VFIMAS : RVI3m<"vfima.s", 0xef, V64, F32>;
1430 // Section 8.15.7 - VFIMS (Vector Floating Iteration Multiply and Subtract)
1431 let cx = 0 in defm VFIMSD : RVI3m<"vfims.d", 0xff, V64, I64>;
1432 let cx = 1 in defm VFIMSS : RVI3m<"vfims.s", 0xff, V64, F32>;
1434 //-----------------------------------------------------------------------------
1435 // Section 8.16 - Vector Merger Operation Instructions
1436 //-----------------------------------------------------------------------------
1438 // Section 8.16.1 - VMRG (Vector Merge)
1439 let cx = 0 in defm VMRG : RVm<"vmrg", 0xd6, V64, I64, VM>;
1441 let cx = 1 in defm VMRGW : RVm<"vmrg.w", 0xd6, V64, I64, VM512>;
1444 // Section 8.16.2 - VSHF (Vector Shuffle)
1447 // Section 8.16.3 - VCP (Vector Compress)
1450 // Section 8.16.4 - VEX (Vector Expand)
1453 //-----------------------------------------------------------------------------
1454 // Section 8.17 - Vector Mask Operation Instructions
1455 //-----------------------------------------------------------------------------
1457 // Section 8.17.1 - VFMK (Vector Form Mask)
1461 // Section 8.17.2 - VFMS (Vector Form Mask Single)
1463 let isCodeGenOnly = 1 in defm PVFMKWLO : RVMKm<"vfmk.w.", 0xb5, V64, VM>;
1464 let cx = 1 in defm PVFMKWUP : RVMKm<"pvfmk.w.up.", 0xb5, V64, VM>;
1468 foreach CC = [ "af", "gt", "lt", "ne", "eq", "ge", "le", "at" ] in {
1472 // Section 8.17.3 - VFMF (Vector Form Mask Floating Point)
1474 let cx2 = 1 in defm PVFMKSLO : RVMKm<"pvfmk.s.lo.", 0xb6, V64, VM>;
1475 let cx = 1 in {
1477 let isCodeGenOnly = 1 in defm VFMKS : RVMKm<"vfmk.s.", 0xb6, V64, VM>;
1484 "gtnan", "ltnan", "nenan", "eqnan", "genan", "lenan" ] in {
1488 // Section 8.17.4 - ANDM (And VM)
1491 // Section 8.17.5 - ORM (Or VM)
1494 // Section 8.17.6 - XORM (Exclusive Or VM)
1497 // Section 8.17.7 - EQVM (Equivalence VM)
1500 // Section 8.17.8 - NNDM (Negate And VM)
1503 // Section 8.17.9 - NEGM (Negate VM)
1506 // Section 8.17.10 - PCVM (Population Count of VM)
1509 // Section 8.17.11 - LZVM (Leading Zero of VM)
1512 // Section 8.17.12 - TOVM (Trailing One of VM)
1515 //-----------------------------------------------------------------------------
1516 // Section 8.18 - Vector Control Instructions
1517 //-----------------------------------------------------------------------------
1519 // Section 8.18.1 - LVL (Load VL)
1520 let sx = 0, cz = 0, sz = 0, hasSideEffects = 0, Defs = [VL] in {
1522 let cy = 0 in def LVLi : RR<0xbf, (outs), (ins simm7:$sy), "lvl $sy">;
1525 // Section 8.18.2 - SVL (Save VL)
1526 let cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0, Uses = [VL] in
1529 // Section 8.18.3 - SMVL (Save Maximum Vector Length)
1530 let cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0 in
1533 // Section 8.18.4 - LVIX (Load Vector Data Index)
1534 let sx = 0, cz = 0, sz = 0, hasSideEffects = 0, Defs = [VIX] in {
1536 let cy = 0 in def LVIXi : RR<0xaf, (outs), (ins uimm6:$sy), "lvix $sy">;